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Searched refs:Q4 (Results 1 – 25 of 25) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/xray/
HDxray_trampoline_AArch64.S27 STP Q4, Q5, [SP, #-32]!
44 LDP Q4, Q5, [SP], #32
115 STP Q4, Q5, [SP, #-32]!
134 LDP Q4, Q5, [SP], #32
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64CallingConvention.td104 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
106 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
108 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
111 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
113 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
146 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
148 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
150 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
153 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
155 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
[all …]
HDAArch64CallingConvention.cpp36 AArch64::Q3, AArch64::Q4, AArch64::Q5,
HDAArch64PBQPRegAlloc.cpp130 case AArch64::Q4: in isOdd()
HDAArch64SchedPredicates.td174 CheckRegOperand<0, Q4>,
HDAArch64RegisterInfo.td392 def Q4 : AArch64Reg<4, "q4", [D4], ["v4", ""]>, DwarfRegAlias<B4>;
753 def Z4 : AArch64Reg<4, "z4", [Q4, Z4_HI]>, DwarfRegNum<[100]>;
HDAArch64FastISel.cpp3017 { AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, in fastLowerArguments()
HDAArch64ISelLowering.cpp3639 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7}; in saveVarArgRegisters()
/freebsd-11-stable/lib/msun/src/
HDs_expm1.c127 Q4 = 4.00821782732936239552e-06, /* 3ED0CFCA 86E65239 */ variable
186 r1 = one+hxs*(Q1+hxs*(Q2+hxs*(Q3+hxs*(Q4+hxs*Q5)))); in expm1()
/freebsd-11-stable/contrib/file/magic/Magdir/
HDpc9855 # XLD4 (Q4) picture
56 11 string/b MAJYO XLD4(Q4) picture
/freebsd-11-stable/lib/msun/bsdsrc/
HDb_tgamma.c106 #define Q4 3.07878176156175520361557573779e-02 macro
254 q = Q0 +z*(Q1+z*(Q2+z*(Q3+z*(Q4+z*(Q5+z*(Q6+z*(Q7+z*Q8)))))));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
HDAArch64MCTargetDesc.cpp199 {codeview::RegisterId::ARM64_Q4, AArch64::Q4}, in initLLVMToCVRegMapping()
HDAArch64InstPrinter.cpp1168 case AArch64::Q3: Reg = AArch64::Q4; break; in getNextVectorRegister()
1169 case AArch64::Q4: Reg = AArch64::Q5; break; in getNextVectorRegister()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMCallingConv.td114 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
HDARMRegisterInfo.td161 def Q4 : ARMReg< 4, "q4", [D8, D9]>;
HDARMInstrInfo.td5701 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/
HDSparcDisassembler.cpp95 SP::Q4, SP::Q12, ~0U, ~0U,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
HDSparcRegisterInfo.td270 def Q4 : Rq<16, "F16", [D8, D9]>;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
HDAArch64Disassembler.cpp305 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
629 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/
HDSparcAsmParser.cpp160 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
HDARMMCCodeEmitter.cpp580 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: in getMachineOpValue()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
HDARMDisassembler.cpp1365 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1383 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
HDAArch64AsmParser.cpp2094 .Case("v4", AArch64::Q4) in MatchNeonVectorRegName()
/freebsd-11-stable/contrib/netbsd-tests/usr.bin/netpgpverify/
HDt_netpgpverify.sh6622 P6V4qKTGqYKWnFClCLpQUzclV4dvnvAC/kNFf1tBdom+Q4+otBFmdpavW0WQ8Wu8
/freebsd-11-stable/usr.bin/fortune/datfiles/
HDfortunes44655 1: P-Q4, Kt-KB3