| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/ |
| HD | XCoreDisassembler.cpp | 647 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
652 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); in DecodeL6RInstruction()
656 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL6RInstruction()
681 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
686 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); in DecodeL5RInstruction()
691 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL5RInstruction()
702 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction() local
707 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
710 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
721 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstSrcDstInstruction() local
[all …]
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| HD | AArch64AsmParser.cpp | 4596 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
4598 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
4600 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); in MatchAndEmitInstruction()
4617 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
4629 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
4639 NewOp4, Op4.getStartLoc(), Op4.getEndLoc(), getContext()); in MatchAndEmitInstruction()
4660 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
4662 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
4664 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); in MatchAndEmitInstruction()
4681 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
[all …]
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| HD | SystemZISelDAGToDAG.cpp | 1564 SDValue Op4 = Node->getOperand(4); in Select() local
1566 CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4); in Select()
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| HD | SelectionDAG.h | 1220 SDValue Op3, SDValue Op4);
1222 SDValue Op3, SDValue Op4, SDValue Op5);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/ |
| HD | PatternMatch.h | 1801 const T4 &Op4) {
1803 m_Argument<4>(Op4));
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| HD | SVEInstrFormats.td | 350 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, vt4:$Op4)),
351 (inst $Op1, $Op2, $Op3, $Op4)>;
367 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, (vt4 ImmTy:$Op4))),
368 (inst $Op1, $Op2, $Op3, ImmTy:$Op4)>;
1739 …def : Pat<(nxv8f16 (op nxv8i1:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, nxv8f16:$Op4, (i32 complexrotateop…
1740 (!cast<Instruction>(NAME # _H) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
1741 …def : Pat<(nxv4f32 (op nxv4i1:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, nxv4f32:$Op4, (i32 complexrotateop…
1742 (!cast<Instruction>(NAME # _S) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
1743 …def : Pat<(nxv2f64 (op nxv2i1:$Op1, nxv2f64:$Op2, nxv2f64:$Op3, nxv2f64:$Op4, (i32 complexrotateop…
1744 (!cast<Instruction>(NAME # _D) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| HD | X86ISelDAGToDAG.cpp | 5278 SDValue Op0, Op1, Op2, Op3, Op4; in SelectInlineAsmMemoryOperand() local
5286 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4)) in SelectInlineAsmMemoryOperand()
5295 OutOps.push_back(Op4); in SelectInlineAsmMemoryOperand()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| HD | ARMAsmParser.cpp | 6422 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]); in tryConvertingToTwoOperandForm() local
6423 if (!Op3.isReg() || !Op4.isReg()) in tryConvertingToTwoOperandForm()
6427 auto Op4Reg = Op4.getReg(); in tryConvertingToTwoOperandForm()
6471 LastOp = &Op4; in tryConvertingToTwoOperandForm()
6492 std::swap(Op4, Op5); in tryConvertingToTwoOperandForm()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| HD | SelectionDAG.cpp | 7678 SDValue Op3, SDValue Op4) { in UpdateNodeOperands() argument
7679 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; in UpdateNodeOperands()
7685 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
7686 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
|
| HD | LegalizeIntegerTypes.cpp | 1732 SDValue Op4 = ZExtPromotedInteger(N->getOperand(4)); in PromoteIntOp_PREFETCH() local
1734 Op2, Op3, Op4), in PromoteIntOp_PREFETCH()
|