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Searched refs:Op0Reg (Results 1 – 4 of 4) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64FastISel.cpp262 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
264 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
266 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
268 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
270 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
272 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
3672 unsigned Op0Reg = getRegForValue(II->getOperand(0)); in fastLowerIntrinsicCall() local
3673 if (!Op0Reg) in fastLowerIntrinsicCall()
3677 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill); in fastLowerIntrinsicCall()
4086 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, in emitLSL_rr() argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsFastISel.cpp1974 unsigned Op0Reg = getRegForValue(Op0); in selectShift() local
1975 if (!Op0Reg) in selectShift()
1986 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt)) in selectShift()
1989 Op0Reg = TempReg; in selectShift()
2009 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal); in selectShift()
2032 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg); in selectShift()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86FastISel.cpp1395 unsigned Op0Reg = getRegForValue(Op0); in X86FastEmitCompare() local
1396 if (Op0Reg == 0) return false; in X86FastEmitCompare()
1408 .addReg(Op0Reg) in X86FastEmitCompare()
1420 .addReg(Op0Reg) in X86FastEmitCompare()
1827 unsigned Op0Reg = getRegForValue(I->getOperand(0)); in X86SelectShift() local
1828 if (Op0Reg == 0) return false; in X86SelectShift()
1844 .addReg(Op0Reg); in X86SelectShift()
1936 unsigned Op0Reg = getRegForValue(I->getOperand(0)); in X86SelectDivRem() local
1937 if (Op0Reg == 0) in X86SelectDivRem()
1945 TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg); in X86SelectDivRem()
HDX86InstructionSelector.cpp1086 const Register Op0Reg = I.getOperand(2).getReg(); in selectUadde() local
1124 .addReg(Op0Reg) in selectUadde()