Searched refs:OP_MASK_RT (Results 1 – 3 of 3) sorted by relevance
877 OP_MASK_RT]); in print_insn_args()885 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()1014 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()1072 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()1080 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()1081 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()1087 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()1174 (l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
75 #define OP_MASK_RT 0x1f macro93 #define OP_MASK_BITIND OP_MASK_RT
8387 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; in validate_mips_insn()8388 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); in validate_mips_insn()8402 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; in validate_mips_insn()8438 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; in validate_mips_insn()8441 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; in validate_mips_insn()8447 USE_BITS (OP_MASK_RT, OP_SH_RT); break; in validate_mips_insn()