Searched refs:NumIntermediates (Results 1 – 9 of 9) sorted by relevance
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| HD | TargetLoweringBase.cpp | 938 unsigned &NumIntermediates, in getVectorTypeBreakdownMVT() argument
961 NumIntermediates = NumVectorRegs; in getVectorTypeBreakdownMVT()
1312 unsigned NumIntermediates; in computeRegisterProperties() local
1314 NumIntermediates, RegisterVT, this); in computeRegisterProperties()
1377 unsigned &NumIntermediates, in getVectorTypeBreakdown() argument
1392 NumIntermediates = 1; in getVectorTypeBreakdown()
1417 NumIntermediates = NumVectorRegs; in getVectorTypeBreakdown()
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| HD | TargetLowering.h | 830 unsigned &NumIntermediates,
838 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv() argument
839 return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates, in getVectorTypeBreakdownForCallingConv()
1292 unsigned NumIntermediates; in getRegisterType() local
1294 NumIntermediates, RegisterVT); in getRegisterType()
1320 unsigned NumIntermediates; in getNumRegisters() local
1321 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); in getNumRegisters()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| HD | SelectionDAGBuilder.cpp | 376 unsigned NumIntermediates; in getCopyFromPartsVector() local
382 NumIntermediates, RegisterVT); in getCopyFromPartsVector()
386 NumIntermediates, RegisterVT); in getCopyFromPartsVector()
397 SmallVector<SDValue, 8> Ops(NumIntermediates); in getCopyFromPartsVector()
398 if (NumIntermediates == NumParts) { in getCopyFromPartsVector()
407 assert(NumParts % NumIntermediates == 0 && in getCopyFromPartsVector()
409 unsigned Factor = NumParts / NumIntermediates; in getCopyFromPartsVector()
410 for (unsigned i = 0; i != NumIntermediates; ++i) in getCopyFromPartsVector()
421 : NumIntermediates)); in getCopyFromPartsVector()
710 unsigned NumIntermediates; in getCopyToPartsVector() local
[all …]
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| HD | SIISelLowering.h | 37 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| HD | SIISelLowering.cpp | 846 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv() argument
854 NumIntermediates = NumElts; in getVectorTypeBreakdownForCallingConv()
855 return NumIntermediates; in getVectorTypeBreakdownForCallingConv()
861 NumIntermediates = NumElts * ((Size + 31) / 32); in getVectorTypeBreakdownForCallingConv()
862 return NumIntermediates; in getVectorTypeBreakdownForCallingConv()
871 NumIntermediates = (NumElts + 1) / 2; in getVectorTypeBreakdownForCallingConv()
872 return NumIntermediates; in getVectorTypeBreakdownForCallingConv()
877 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| HD | MipsISelLowering.h | 304 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| HD | MipsISelLowering.cpp | 133 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv() argument
137 NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits() in getVectorTypeBreakdownForCallingConv()
141 return NumIntermediates; in getVectorTypeBreakdownForCallingConv()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| HD | X86ISelLowering.h | 1248 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| HD | X86ISelLowering.cpp | 2138 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv() argument
2147 NumIntermediates = VT.getVectorNumElements(); in getVectorTypeBreakdownForCallingConv()
2148 return NumIntermediates; in getVectorTypeBreakdownForCallingConv()
2156 NumIntermediates = 2; in getVectorTypeBreakdownForCallingConv()
2161 NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
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