1 /*-
2 * Copyright (C) 2012-2014 Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29 #ifndef __NVME_PRIVATE_H__
30 #define __NVME_PRIVATE_H__
31
32 #include <sys/param.h>
33 #include <sys/bio.h>
34 #include <sys/bus.h>
35 #include <sys/kernel.h>
36 #include <sys/lock.h>
37 #include <sys/malloc.h>
38 #include <sys/mutex.h>
39 #include <sys/rman.h>
40 #include <sys/systm.h>
41 #include <sys/taskqueue.h>
42
43 #include <vm/uma.h>
44
45 #include <machine/bus.h>
46
47 #include "nvme.h"
48
49 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev))
50
51 MALLOC_DECLARE(M_NVME);
52
53 #define IDT32_PCI_ID 0x80d0111d /* 32 channel board */
54 #define IDT8_PCI_ID 0x80d2111d /* 8 channel board */
55
56 /*
57 * For commands requiring more than 2 PRP entries, one PRP will be
58 * embedded in the command (prp1), and the rest of the PRP entries
59 * will be in a list pointed to by the command (prp2). This means
60 * that real max number of PRP entries we support is 32+1, which
61 * results in a max xfer size of 32*PAGE_SIZE.
62 */
63 #define NVME_MAX_PRP_LIST_ENTRIES (NVME_MAX_XFER_SIZE / PAGE_SIZE)
64
65 #define NVME_ADMIN_TRACKERS (16)
66 #define NVME_ADMIN_ENTRIES (128)
67 /* min and max are defined in admin queue attributes section of spec */
68 #define NVME_MIN_ADMIN_ENTRIES (2)
69 #define NVME_MAX_ADMIN_ENTRIES (4096)
70
71 /*
72 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion
73 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we
74 * will allow outstanding on an I/O qpair at any time. The only advantage in
75 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping
76 * the contents of the submission and completion queues, it will show a longer
77 * history of data.
78 */
79 #define NVME_IO_ENTRIES (256)
80 #define NVME_IO_TRACKERS (128)
81 #define NVME_MIN_IO_TRACKERS (4)
82 #define NVME_MAX_IO_TRACKERS (1024)
83
84 /*
85 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES
86 * for each controller.
87 */
88
89 #define NVME_INT_COAL_TIME (0) /* disabled */
90 #define NVME_INT_COAL_THRESHOLD (0) /* 0-based */
91
92 #define NVME_MAX_NAMESPACES (16)
93 #define NVME_MAX_CONSUMERS (2)
94 #define NVME_MAX_ASYNC_EVENTS (8)
95
96 #define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */
97 #define NVME_MIN_TIMEOUT_PERIOD (5)
98 #define NVME_MAX_TIMEOUT_PERIOD (120)
99
100 #define NVME_DEFAULT_RETRY_COUNT (4)
101
102 /* Maximum log page size to fetch for AERs. */
103 #define NVME_MAX_AER_LOG_SIZE (4096)
104
105 /*
106 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define
107 * it.
108 */
109 #ifndef CACHE_LINE_SIZE
110 #define CACHE_LINE_SIZE (64)
111 #endif
112
113 extern uma_zone_t nvme_request_zone;
114 extern int32_t nvme_retry_count;
115
116 struct nvme_completion_poll_status {
117
118 struct nvme_completion cpl;
119 int done;
120 };
121
122 #define NVME_REQUEST_VADDR 1
123 #define NVME_REQUEST_NULL 2 /* For requests with no payload. */
124 #define NVME_REQUEST_UIO 3
125 #define NVME_REQUEST_BIO 4
126 #define NVME_REQUEST_CCB 5
127
128 struct nvme_request {
129
130 struct nvme_command cmd;
131 struct nvme_qpair *qpair;
132 union {
133 void *payload;
134 struct bio *bio;
135 } u;
136 uint32_t type;
137 uint32_t payload_size;
138 boolean_t timeout;
139 nvme_cb_fn_t cb_fn;
140 void *cb_arg;
141 int32_t retries;
142 STAILQ_ENTRY(nvme_request) stailq;
143 };
144
145 struct nvme_async_event_request {
146
147 struct nvme_controller *ctrlr;
148 struct nvme_request *req;
149 struct nvme_completion cpl;
150 uint32_t log_page_id;
151 uint32_t log_page_size;
152 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE];
153 };
154
155 struct nvme_tracker {
156
157 TAILQ_ENTRY(nvme_tracker) tailq;
158 struct nvme_request *req;
159 struct nvme_qpair *qpair;
160 struct callout timer;
161 bus_dmamap_t payload_dma_map;
162 uint16_t cid;
163
164 uint64_t *prp;
165 bus_addr_t prp_bus_addr;
166 };
167
168 struct nvme_qpair {
169
170 struct nvme_controller *ctrlr;
171 uint32_t id;
172 uint32_t phase;
173
174 uint16_t vector;
175 int rid;
176 struct resource *res;
177 void *tag;
178
179 uint32_t num_entries;
180 uint32_t num_trackers;
181 uint32_t sq_tdbl_off;
182 uint32_t cq_hdbl_off;
183
184 uint32_t sq_head;
185 uint32_t sq_tail;
186 uint32_t cq_head;
187
188 int64_t num_cmds;
189 int64_t num_intr_handler_calls;
190
191 struct nvme_command *cmd;
192 struct nvme_completion *cpl;
193
194 bus_dma_tag_t dma_tag;
195 bus_dma_tag_t dma_tag_payload;
196
197 bus_dmamap_t queuemem_map;
198 uint64_t cmd_bus_addr;
199 uint64_t cpl_bus_addr;
200
201 TAILQ_HEAD(, nvme_tracker) free_tr;
202 TAILQ_HEAD(, nvme_tracker) outstanding_tr;
203 STAILQ_HEAD(, nvme_request) queued_req;
204
205 struct nvme_tracker **act_tr;
206
207 boolean_t is_enabled;
208
209 struct mtx lock __aligned(CACHE_LINE_SIZE);
210
211 } __aligned(CACHE_LINE_SIZE);
212
213 struct nvme_namespace {
214
215 struct nvme_controller *ctrlr;
216 struct nvme_namespace_data data;
217 uint32_t id;
218 uint32_t flags;
219 struct cdev *cdev;
220 void *cons_cookie[NVME_MAX_CONSUMERS];
221 uint32_t stripesize;
222 struct mtx lock;
223 };
224
225 /*
226 * One of these per allocated PCI device.
227 */
228 struct nvme_controller {
229
230 device_t dev;
231
232 struct mtx lock;
233
234 uint32_t ready_timeout_in_ms;
235 uint32_t quirks;
236 #define QUIRK_DELAY_B4_CHK_RDY 1 /* Can't touch MMIO on disable */
237 #define QUIRK_DISABLE_TIMEOUT 2 /* Disable broken completion timeout feature */
238
239 bus_space_tag_t bus_tag;
240 bus_space_handle_t bus_handle;
241 int resource_id;
242 struct resource *resource;
243
244 /*
245 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5,
246 * separate from the control registers which are in BAR 0/1. These
247 * members track the mapping of BAR 4/5 for that reason.
248 */
249 int bar4_resource_id;
250 struct resource *bar4_resource;
251
252 uint32_t msix_enabled;
253 uint32_t force_intx;
254 uint32_t enable_aborts;
255
256 uint32_t num_io_queues;
257 uint32_t num_cpus_per_ioq;
258 uint32_t max_hw_pend_io;
259
260 /* Fields for tracking progress during controller initialization. */
261 struct intr_config_hook config_hook;
262 uint32_t ns_identified;
263 uint32_t queues_created;
264
265 struct task reset_task;
266 struct task fail_req_task;
267 struct taskqueue *taskqueue;
268
269 /* For shared legacy interrupt. */
270 int rid;
271 struct resource *res;
272 void *tag;
273
274 bus_dma_tag_t hw_desc_tag;
275 bus_dmamap_t hw_desc_map;
276
277 /** maximum i/o size in bytes */
278 uint32_t max_xfer_size;
279
280 /** minimum page size supported by this controller in bytes */
281 uint32_t min_page_size;
282
283 /** interrupt coalescing time period (in microseconds) */
284 uint32_t int_coal_time;
285
286 /** interrupt coalescing threshold */
287 uint32_t int_coal_threshold;
288
289 /** timeout period in seconds */
290 uint32_t timeout_period;
291
292 struct nvme_qpair adminq;
293 struct nvme_qpair *ioq;
294
295 struct nvme_registers *regs;
296
297 struct nvme_controller_data cdata;
298 struct nvme_namespace ns[NVME_MAX_NAMESPACES];
299
300 struct cdev *cdev;
301
302 /** bit mask of warning types currently enabled for async events */
303 union nvme_critical_warning_state async_event_config;
304
305 uint32_t num_aers;
306 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS];
307
308 void *cons_cookie[NVME_MAX_CONSUMERS];
309
310 uint32_t is_resetting;
311 uint32_t is_initialized;
312 uint32_t notification_sent;
313
314 boolean_t is_failed;
315 STAILQ_HEAD(, nvme_request) fail_req;
316 };
317
318 #define nvme_mmio_offsetof(reg) \
319 offsetof(struct nvme_registers, reg)
320
321 #define nvme_mmio_read_4(sc, reg) \
322 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \
323 nvme_mmio_offsetof(reg))
324
325 #define nvme_mmio_write_4(sc, reg, val) \
326 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
327 nvme_mmio_offsetof(reg), val)
328
329 #define nvme_mmio_write_8(sc, reg, val) \
330 do { \
331 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
332 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \
333 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
334 nvme_mmio_offsetof(reg)+4, \
335 (val & 0xFFFFFFFF00000000UL) >> 32); \
336 } while (0);
337
338 #define nvme_printf(ctrlr, fmt, args...) \
339 device_printf(ctrlr->dev, fmt, ##args)
340
341 void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg);
342
343 void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr,
344 void *payload,
345 nvme_cb_fn_t cb_fn, void *cb_arg);
346 void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr,
347 uint32_t nsid, void *payload,
348 nvme_cb_fn_t cb_fn, void *cb_arg);
349 void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr,
350 uint32_t microseconds,
351 uint32_t threshold,
352 nvme_cb_fn_t cb_fn,
353 void *cb_arg);
354 void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr,
355 struct nvme_error_information_entry *payload,
356 uint32_t num_entries, /* 0 = max */
357 nvme_cb_fn_t cb_fn,
358 void *cb_arg);
359 void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr,
360 uint32_t nsid,
361 struct nvme_health_information_page *payload,
362 nvme_cb_fn_t cb_fn,
363 void *cb_arg);
364 void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr,
365 struct nvme_firmware_page *payload,
366 nvme_cb_fn_t cb_fn,
367 void *cb_arg);
368 void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr,
369 struct nvme_qpair *io_que, uint16_t vector,
370 nvme_cb_fn_t cb_fn, void *cb_arg);
371 void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr,
372 struct nvme_qpair *io_que,
373 nvme_cb_fn_t cb_fn, void *cb_arg);
374 void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr,
375 struct nvme_qpair *io_que,
376 nvme_cb_fn_t cb_fn, void *cb_arg);
377 void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr,
378 struct nvme_qpair *io_que,
379 nvme_cb_fn_t cb_fn, void *cb_arg);
380 void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr,
381 uint32_t num_queues, nvme_cb_fn_t cb_fn,
382 void *cb_arg);
383 void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr,
384 union nvme_critical_warning_state state,
385 nvme_cb_fn_t cb_fn, void *cb_arg);
386 void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid,
387 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg);
388
389 void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl);
390
391 int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev);
392 void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev);
393 void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr);
394 int nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr);
395 void nvme_ctrlr_reset(struct nvme_controller *ctrlr);
396 /* ctrlr defined as void * to allow use with config_intrhook. */
397 void nvme_ctrlr_start_config_hook(void *ctrlr_arg);
398 void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr,
399 struct nvme_request *req);
400 void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr,
401 struct nvme_request *req);
402 void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr,
403 struct nvme_request *req);
404
405 int nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id,
406 uint16_t vector, uint32_t num_entries,
407 uint32_t num_trackers,
408 struct nvme_controller *ctrlr);
409 void nvme_qpair_submit_tracker(struct nvme_qpair *qpair,
410 struct nvme_tracker *tr);
411 bool nvme_qpair_process_completions(struct nvme_qpair *qpair);
412 void nvme_qpair_submit_request(struct nvme_qpair *qpair,
413 struct nvme_request *req);
414 void nvme_qpair_reset(struct nvme_qpair *qpair);
415 void nvme_qpair_fail(struct nvme_qpair *qpair);
416 void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair,
417 struct nvme_request *req,
418 uint32_t sct, uint32_t sc);
419
420 void nvme_admin_qpair_enable(struct nvme_qpair *qpair);
421 void nvme_admin_qpair_disable(struct nvme_qpair *qpair);
422 void nvme_admin_qpair_destroy(struct nvme_qpair *qpair);
423
424 void nvme_io_qpair_enable(struct nvme_qpair *qpair);
425 void nvme_io_qpair_disable(struct nvme_qpair *qpair);
426 void nvme_io_qpair_destroy(struct nvme_qpair *qpair);
427
428 int nvme_ns_construct(struct nvme_namespace *ns, uint32_t id,
429 struct nvme_controller *ctrlr);
430 void nvme_ns_destruct(struct nvme_namespace *ns);
431
432 void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr);
433
434 void nvme_dump_command(struct nvme_command *cmd);
435 void nvme_dump_completion(struct nvme_completion *cpl);
436
437 static __inline void
nvme_single_map(void * arg,bus_dma_segment_t * seg,int nseg,int error)438 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
439 {
440 uint64_t *bus_addr = (uint64_t *)arg;
441
442 if (error != 0)
443 printf("nvme_single_map err %d\n", error);
444 *bus_addr = seg[0].ds_addr;
445 }
446
447 static __inline struct nvme_request *
_nvme_allocate_request(nvme_cb_fn_t cb_fn,void * cb_arg)448 _nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg)
449 {
450 struct nvme_request *req;
451
452 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO);
453 if (req != NULL) {
454 req->cb_fn = cb_fn;
455 req->cb_arg = cb_arg;
456 req->timeout = TRUE;
457 }
458 return (req);
459 }
460
461 static __inline struct nvme_request *
nvme_allocate_request_vaddr(void * payload,uint32_t payload_size,nvme_cb_fn_t cb_fn,void * cb_arg)462 nvme_allocate_request_vaddr(void *payload, uint32_t payload_size,
463 nvme_cb_fn_t cb_fn, void *cb_arg)
464 {
465 struct nvme_request *req;
466
467 req = _nvme_allocate_request(cb_fn, cb_arg);
468 if (req != NULL) {
469 req->type = NVME_REQUEST_VADDR;
470 req->u.payload = payload;
471 req->payload_size = payload_size;
472 }
473 return (req);
474 }
475
476 static __inline struct nvme_request *
nvme_allocate_request_null(nvme_cb_fn_t cb_fn,void * cb_arg)477 nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg)
478 {
479 struct nvme_request *req;
480
481 req = _nvme_allocate_request(cb_fn, cb_arg);
482 if (req != NULL)
483 req->type = NVME_REQUEST_NULL;
484 return (req);
485 }
486
487 static __inline struct nvme_request *
nvme_allocate_request_bio(struct bio * bio,nvme_cb_fn_t cb_fn,void * cb_arg)488 nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg)
489 {
490 struct nvme_request *req;
491
492 req = _nvme_allocate_request(cb_fn, cb_arg);
493 if (req != NULL) {
494 req->type = NVME_REQUEST_BIO;
495 req->u.bio = bio;
496 }
497 return (req);
498 }
499
500 static __inline struct nvme_request *
nvme_allocate_request_ccb(union ccb * ccb,nvme_cb_fn_t cb_fn,void * cb_arg)501 nvme_allocate_request_ccb(union ccb *ccb, nvme_cb_fn_t cb_fn, void *cb_arg)
502 {
503 struct nvme_request *req;
504
505 req = _nvme_allocate_request(cb_fn, cb_arg);
506 if (req != NULL) {
507 req->type = NVME_REQUEST_CCB;
508 req->u.payload = ccb;
509 }
510
511 return (req);
512 }
513
514 #define nvme_free_request(req) uma_zfree(nvme_request_zone, req)
515
516 void nvme_notify_async_consumers(struct nvme_controller *ctrlr,
517 const struct nvme_completion *async_cpl,
518 uint32_t log_page_id, void *log_page_buffer,
519 uint32_t log_page_size);
520 void nvme_notify_fail_consumers(struct nvme_controller *ctrlr);
521 void nvme_notify_new_controller(struct nvme_controller *ctrlr);
522
523 void nvme_ctrlr_intx_handler(void *arg);
524 void nvme_ctrlr_poll(struct nvme_controller *ctrlr);
525
526 #endif /* __NVME_PRIVATE_H__ */
527