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Searched refs:Mips (Results 1 – 25 of 104) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsSEInstrInfo.cpp29 return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM; in getUnconditionalBranch()
30 return STI.isPositionIndependent() ? Mips::B : Mips::J; in getUnconditionalBranch()
49 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
71 if ((Opc == Mips::SW) || (Opc == Mips::SD) || in isStoreToStackSlot()
72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
91 if (Mips::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
93 Opc = Mips::MOVE16_MM; in copyPhysReg()
95 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
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HDMipsInstrInfo.cpp40 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), in MipsInstrInfo()
61 BuildMI(MBB, MI, DL, get(Mips::NOP)); in insertNoop()
281 case Mips::B: in isBranchOffsetInRange()
282 case Mips::BAL: in isBranchOffsetInRange()
283 case Mips::BAL_BR: in isBranchOffsetInRange()
284 case Mips::BAL_BR_MM: in isBranchOffsetInRange()
285 case Mips::BC1F: in isBranchOffsetInRange()
286 case Mips::BC1FL: in isBranchOffsetInRange()
287 case Mips::BC1T: in isBranchOffsetInRange()
288 case Mips::BC1TL: in isBranchOffsetInRange()
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HDMipsExpandPseudo.cpp84 unsigned ZERO = Mips::ZERO; in expandAtomicCmpSwapSubword()
85 unsigned BNE = Mips::BNE; in expandAtomicCmpSwapSubword()
86 unsigned BEQ = Mips::BEQ; in expandAtomicCmpSwapSubword()
88 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I8_POSTRA ? Mips::SEB : Mips::SEH; in expandAtomicCmpSwapSubword()
91 LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM; in expandAtomicCmpSwapSubword()
92 SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM; in expandAtomicCmpSwapSubword()
93 BNE = STI->hasMips32r6() ? Mips::BNEC_MMR6 : Mips::BNE_MM; in expandAtomicCmpSwapSubword()
94 BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM; in expandAtomicCmpSwapSubword()
96 LL = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) in expandAtomicCmpSwapSubword()
97 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); in expandAtomicCmpSwapSubword()
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HDMips16InstrInfo.cpp43 : MipsInstrInfo(STI, Mips::Bimm16) {} in Mips16InstrInfo()
75 if (Mips::CPU16RegsRegClass.contains(DestReg) && in copyPhysReg()
76 Mips::GPR32RegClass.contains(SrcReg)) in copyPhysReg()
77 Opc = Mips::MoveR3216; in copyPhysReg()
78 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
79 Mips::CPU16RegsRegClass.contains(SrcReg)) in copyPhysReg()
80 Opc = Mips::Move32R16; in copyPhysReg()
81 else if ((SrcReg == Mips::HI0) && in copyPhysReg()
82 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
83 Opc = Mips::Mfhi16, SrcReg = 0; in copyPhysReg()
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HDMicroMipsSizeReduction.cpp214 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),
216 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,
218 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUR1SP_MM),
220 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUSP_MM),
222 {RT_OneInstr, OpCodes(Mips::ADDu, Mips::ADDU16_MM),
225 {RT_OneInstr, OpCodes(Mips::ADDu_MM, Mips::ADDU16_MM),
228 {RT_OneInstr, OpCodes(Mips::LBu, Mips::LBU16_MM), ReduceLXUtoLXU16,
230 {RT_OneInstr, OpCodes(Mips::LBu_MM, Mips::LBU16_MM), ReduceLXUtoLXU16,
232 {RT_OneInstr, OpCodes(Mips::LEA_ADDiu, Mips::ADDIUR1SP_MM),
234 {RT_OneInstr, OpCodes(Mips::LEA_ADDiu_MM, Mips::ADDIUR1SP_MM),
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HDMipsRegisterInfo.cpp42 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {} in MipsRegisterInfo()
44 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; } in getPICCallReg()
54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
56 return &Mips::GPRMM16RegClass; in getPointerRegClass()
58 return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass; in getPointerRegClass()
60 return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass; in getPointerRegClass()
72 case Mips::GPR32RegClassID: in getRegPressureLimit()
73 case Mips::GPR64RegClassID: in getRegPressureLimit()
74 case Mips::DSPRRegClassID: { in getRegPressureLimit()
78 case Mips::FGR32RegClassID: in getRegPressureLimit()
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HDMipsRegisterBankInfo.cpp26 namespace Mips { namespace
82 using namespace Mips; in getRegBankFromRegClass()
85 case Mips::GPR32RegClassID: in getRegBankFromRegClass()
86 case Mips::CPU16Regs_and_GPRMM16ZeroRegClassID: in getRegBankFromRegClass()
87 case Mips::GPRMM16MovePPairFirstRegClassID: in getRegBankFromRegClass()
88 case Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID: in getRegBankFromRegClass()
89 case Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID: in getRegBankFromRegClass()
90 case Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID: in getRegBankFromRegClass()
91 case Mips::SP32RegClassID: in getRegBankFromRegClass()
92 case Mips::GP32RegClassID: in getRegBankFromRegClass()
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HDMipsSERegisterInfo.cpp56 return &Mips::GPR32RegClass; in intRegClass()
59 return &Mips::GPR64RegClass; in intRegClass()
68 case Mips::LD_B: in getLoadStoreOffsetSizeInBits()
69 case Mips::ST_B: in getLoadStoreOffsetSizeInBits()
71 case Mips::LD_H: in getLoadStoreOffsetSizeInBits()
72 case Mips::ST_H: in getLoadStoreOffsetSizeInBits()
74 case Mips::LD_W: in getLoadStoreOffsetSizeInBits()
75 case Mips::ST_W: in getLoadStoreOffsetSizeInBits()
77 case Mips::LD_D: in getLoadStoreOffsetSizeInBits()
78 case Mips::ST_D: in getLoadStoreOffsetSizeInBits()
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HDMipsBranchExpansion.cpp371 unsigned JR = ABI.IsN64() ? Mips::JR64 : Mips::JR; in buildProperJumpMI()
372 unsigned JIC = ABI.IsN64() ? Mips::JIC64 : Mips::JIC; in buildProperJumpMI()
373 unsigned JR_HB = ABI.IsN64() ? Mips::JR_HB64 : Mips::JR_HB; in buildProperJumpMI()
374 unsigned JR_HB_R6 = ABI.IsN64() ? Mips::JR_HB64_R6 : Mips::JR_HB_R6; in buildProperJumpMI()
382 if (JumpOp == Mips::JIC && STI->inMicroMipsMode()) in buildProperJumpMI()
383 JumpOp = Mips::JIC_MMR6; in buildProperJumpMI()
385 unsigned ATReg = ABI.IsN64() ? Mips::AT_64 : Mips::AT; in buildProperJumpMI()
421 ? STI->inMicroMipsMode() ? Mips::BALC_MMR6 : Mips::BALC in expandToLongBranch()
422 : STI->inMicroMipsMode() ? Mips::BAL_BR_MM : Mips::BAL_BR; in expandToLongBranch()
456 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
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HDMips16ISelLowering.cpp125 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); in Mips16TargetLowering()
169 case Mips::SelBeqZ: in EmitInstrWithCustomInserter()
170 return emitSel16(Mips::BeqzRxImm16, MI, BB); in EmitInstrWithCustomInserter()
171 case Mips::SelBneZ: in EmitInstrWithCustomInserter()
172 return emitSel16(Mips::BnezRxImm16, MI, BB); in EmitInstrWithCustomInserter()
173 case Mips::SelTBteqZCmpi: in EmitInstrWithCustomInserter()
174 return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB); in EmitInstrWithCustomInserter()
175 case Mips::SelTBteqZSlti: in EmitInstrWithCustomInserter()
176 return emitSeliT16(Mips::Bteqz16, Mips::SltiRxImmX16, MI, BB); in EmitInstrWithCustomInserter()
177 case Mips::SelTBteqZSltiu: in EmitInstrWithCustomInserter()
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HDMipsInstructionSelector.cpp91 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID; in isRegInGprb()
96 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID; in isRegInFprb()
122 return &Mips::GPR32RegClass; in getRegClassForTypeOnBank()
130 return &Mips::FGR32RegClass; in getRegClassForTypeOnBank()
131 return STI.isFP64bit() ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in getRegClassForTypeOnBank()
144 B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
150 MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {}) in materialize32BitImm()
157 B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
162 Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass); in materialize32BitImm()
163 MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {}) in materialize32BitImm()
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HDMipsSEFrameLowering.cpp50 if (Mips::ACC64RegClass.contains(Src)) in getMFHiLoOpc()
51 return std::make_pair((unsigned)Mips::PseudoMFHI, in getMFHiLoOpc()
52 (unsigned)Mips::PseudoMFLO); in getMFHiLoOpc()
54 if (Mips::ACC64DSPRegClass.contains(Src)) in getMFHiLoOpc()
55 return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP); in getMFHiLoOpc()
57 if (Mips::ACC128RegClass.contains(Src)) in getMFHiLoOpc()
58 return std::make_pair((unsigned)Mips::PseudoMFHI64, in getMFHiLoOpc()
59 (unsigned)Mips::PseudoMFLO64); in getMFHiLoOpc()
117 case Mips::LOAD_CCOND_DSP: in expandInstr()
120 case Mips::STORE_CCOND_DSP: in expandInstr()
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HDMipsAsmPrinter.cpp123 TmpInst0.setOpcode(Mips::JALR64); in emitPseudoIndirectBranch()
128 TmpInst0.setOpcode(Mips::JRC16_MMR6); in emitPseudoIndirectBranch()
130 TmpInst0.setOpcode(Mips::JALR); in emitPseudoIndirectBranch()
135 TmpInst0.setOpcode(Mips::JR_MM); in emitPseudoIndirectBranch()
138 TmpInst0.setOpcode(Mips::JR); in emitPseudoIndirectBranch()
144 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch()
204 if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) { in EmitInstruction()
208 if (Opc == Mips::CONSTPOOL_ENTRY) { in EmitInstruction()
236 case Mips::PATCHABLE_FUNCTION_ENTER: in EmitInstruction()
239 case Mips::PATCHABLE_FUNCTION_EXIT: in EmitInstruction()
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HDMipsFastISel.cpp305 Opc = Mips::AND; in emitLogicalOp()
308 Opc = Mips::OR; in emitLogicalOp()
311 Opc = Mips::XOR; in emitLogicalOp()
329 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp()
345 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in fastMaterializeAlloca()
346 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu), in fastMaterializeAlloca()
359 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeInt()
369 unsigned Opc = Mips::ADDiu; in materialize32BitInt()
370 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
373 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
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HDMipsSEISelDAGToDAG.cpp60 MIB.addReg(Mips::DSPPos, Flag); in addDSPCtrlRegOperands()
63 MIB.addReg(Mips::DSPSCount, Flag); in addDSPCtrlRegOperands()
66 MIB.addReg(Mips::DSPCarry, Flag); in addDSPCtrlRegOperands()
69 MIB.addReg(Mips::DSPOutFlag, Flag); in addDSPCtrlRegOperands()
72 MIB.addReg(Mips::DSPCCond, Flag); in addDSPCtrlRegOperands()
75 MIB.addReg(Mips::DSPEFI, Flag); in addDSPCtrlRegOperands()
80 return Mips::MSACtrlRegClass.getRegister(RegNum); in getMSACtrlReg()
88 if ((MI.getOpcode() == Mips::ADDiu) && in replaceUsesWithZeroReg()
89 (MI.getOperand(1).getReg() == Mips::ZERO) && in replaceUsesWithZeroReg()
93 ZeroReg = Mips::ZERO; in replaceUsesWithZeroReg()
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HDMipsMachineFunction.cpp36 return Mips::CPU16RegsRegClass; in getGlobalBaseRegClass()
39 return Mips::GPRMM16RegClass; in getGlobalBaseRegClass()
42 return Mips::GPR64RegClass; in getGlobalBaseRegClass()
44 return Mips::GPR32RegClass; in getGlobalBaseRegClass()
75 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
81 MF.getRegInfo().addLiveIn(Mips::T9_64); in initGlobalBaseReg()
82 MBB.addLiveIn(Mips::T9_64); in initGlobalBaseReg()
88 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) in initGlobalBaseReg()
90 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0) in initGlobalBaseReg()
91 .addReg(Mips::T9_64); in initGlobalBaseReg()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
HDMipsAsmBackend.cpp48 case Mips::fixup_Mips_LO16: in adjustFixupValue()
49 case Mips::fixup_Mips_GPREL16: in adjustFixupValue()
50 case Mips::fixup_Mips_GPOFF_HI: in adjustFixupValue()
51 case Mips::fixup_Mips_GPOFF_LO: in adjustFixupValue()
52 case Mips::fixup_Mips_GOT_PAGE: in adjustFixupValue()
53 case Mips::fixup_Mips_GOT_OFST: in adjustFixupValue()
54 case Mips::fixup_Mips_GOT_DISP: in adjustFixupValue()
55 case Mips::fixup_Mips_GOT_LO16: in adjustFixupValue()
56 case Mips::fixup_Mips_CALL_LO16: in adjustFixupValue()
57 case Mips::fixup_MICROMIPS_GPOFF_HI: in adjustFixupValue()
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HDMipsABIInfo.cpp26 static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
29 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
30 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
75 return ArePtrs64bit() ? Mips::SP_64 : Mips::SP; in GetStackPtr()
79 return ArePtrs64bit() ? Mips::FP_64 : Mips::FP; in GetFramePtr()
83 return ArePtrs64bit() ? Mips::S7_64 : Mips::S7; in GetBasePtr()
87 return ArePtrs64bit() ? Mips::GP_64 : Mips::GP; in GetGlobalPtr()
91 return ArePtrs64bit() ? Mips::ZERO_64 : Mips::ZERO; in GetNullPtr()
95 return AreGprs64bit() ? Mips::ZERO_64 : Mips::ZERO; in GetZeroReg()
99 return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu; in GetPtrAdduOp()
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HDMipsMCCodeEmitter.cpp76 case Mips::DSLL: in LowerLargeShift()
77 Inst.setOpcode(Mips::DSLL32); in LowerLargeShift()
79 case Mips::DSRL: in LowerLargeShift()
80 Inst.setOpcode(Mips::DSRL32); in LowerLargeShift()
82 case Mips::DSRA: in LowerLargeShift()
83 Inst.setOpcode(Mips::DSRA32); in LowerLargeShift()
85 case Mips::DROTR: in LowerLargeShift()
86 Inst.setOpcode(Mips::DROTR32); in LowerLargeShift()
101 if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC || in LowerCompactBranch()
102 Inst.getOpcode() == Mips::BNEC64 || Inst.getOpcode() == Mips::BEQC64) { in LowerCompactBranch()
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HDMipsInstPrinter.cpp36 const char* Mips::MipsFCCToString(Mips::CondCode CC) { in MipsFCCToString()
84 case Mips::RDHWR: in printInst()
85 case Mips::RDHWR64: in printInst()
89 case Mips::Save16: in printInst()
94 case Mips::SaveX16: in printInst()
99 case Mips::Restore16: in printInst()
104 case Mips::RestoreX16: in printInst()
119 case Mips::RDHWR: in printInst()
120 case Mips::RDHWR64: in printInst()
168 case Mips::SWM32_MM: in printMemOperand()
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HDMipsNaClELFStreamer.cpp37 const unsigned IndirectBranchMaskReg = Mips::T6;
38 const unsigned LoadStoreStackMaskReg = Mips::T7;
59 if (MI.getOpcode() == Mips::JALR) { in isIndirectJump()
63 return MI.getOperand(0).getReg() == Mips::ZERO; in isIndirectJump()
65 return MI.getOpcode() == Mips::JR; in isIndirectJump()
70 && MI.getOperand(0).getReg() == Mips::SP); in isStackPointerFirstOperand()
82 case Mips::JAL: in isCall()
83 case Mips::BAL: in isCall()
84 case Mips::BAL_BR: in isCall()
85 case Mips::BLTZAL: in isCall()
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HDMipsELFObjectWriter.cpp231 case Mips::fixup_Mips_16: in getRelocType()
234 case Mips::fixup_Mips_32: in getRelocType()
245 case Mips::fixup_Mips_Branch_PCRel: in getRelocType()
246 case Mips::fixup_Mips_PC16: in getRelocType()
248 case Mips::fixup_MICROMIPS_PC7_S1: in getRelocType()
250 case Mips::fixup_MICROMIPS_PC10_S1: in getRelocType()
252 case Mips::fixup_MICROMIPS_PC16_S1: in getRelocType()
254 case Mips::fixup_MICROMIPS_PC26_S1: in getRelocType()
256 case Mips::fixup_MICROMIPS_PC19_S2: in getRelocType()
258 case Mips::fixup_MICROMIPS_PC18_S3: in getRelocType()
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HDMipsABIFlagsSection.h32 Mips::AFL_REG GPRSize = Mips::AFL_REG_NONE;
34 Mips::AFL_REG CPR1Size = Mips::AFL_REG_NONE;
36 Mips::AFL_REG CPR2Size = Mips::AFL_REG_NONE;
38 Mips::AFL_EXT ISAExtension = Mips::AFL_EXT_NONE;
67 Value |= (uint32_t)Mips::AFL_FLAGS1_ODDSPREG; in getFlags1Value()
127 GPRSize = P.isGP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32; in setGPRSizeFromPredicates()
133 CPR1Size = Mips::AFL_REG_NONE; in setCPR1SizeFromPredicates()
135 CPR1Size = Mips::AFL_REG_128; in setCPR1SizeFromPredicates()
137 CPR1Size = P.isFP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32; in setCPR1SizeFromPredicates()
143 ISAExtension = Mips::AFL_EXT_OCTEONP; in setISAExtensionFromPredicates()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
HDMipsAsmParser.cpp122 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
123 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
124 Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
125 Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
126 Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
127 Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
128 Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
129 Mips::FeatureCnMipsP, Mips::FeatureFP64Bit, Mips::FeatureGP64Bit,
130 Mips::FeatureNaN2008
561 return getSTI().getFeatureBits()[Mips::FeatureGP64Bit]; in isGP64bit()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
HDMipsDisassembler.cpp47 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), in MipsDisassembler()
50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } in hasMips2()
51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } in hasMips3()
52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } in hasMips32()
55 return STI.getFeatureBits()[Mips::FeatureMips32r6]; in hasMips32r6()
58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } in isFP64()
60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } in isGP64()
62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } in isPTR64()
64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } in hasCnMips()
66 bool hasCnMipsP() const { return STI.getFeatureBits()[Mips::FeatureCnMipsP]; } in hasCnMipsP()
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