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Searched refs:MVT (Results 1 – 25 of 244) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86TargetTransformInfo.cpp180 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); in getArithmeticInstrCost()
186 { ISD::FDIV, MVT::f32, 18 }, // divss in getArithmeticInstrCost()
187 { ISD::FDIV, MVT::v4f32, 35 }, // divps in getArithmeticInstrCost()
188 { ISD::FDIV, MVT::f64, 33 }, // divsd in getArithmeticInstrCost()
189 { ISD::FDIV, MVT::v2f64, 65 }, // divpd in getArithmeticInstrCost()
198 { ISD::MUL, MVT::v4i32, 11 }, // pmulld in getArithmeticInstrCost()
199 { ISD::MUL, MVT::v8i16, 2 }, // pmullw in getArithmeticInstrCost()
200 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. in getArithmeticInstrCost()
201 { ISD::FMUL, MVT::f64, 2 }, // mulsd in getArithmeticInstrCost()
202 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd in getArithmeticInstrCost()
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HDX86ISelLowering.cpp115 MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0)); in X86TargetLowering()
173 addRegisterClass(MVT::i8, &X86::GR8RegClass); in X86TargetLowering()
174 addRegisterClass(MVT::i16, &X86::GR16RegClass); in X86TargetLowering()
175 addRegisterClass(MVT::i32, &X86::GR32RegClass); in X86TargetLowering()
177 addRegisterClass(MVT::i64, &X86::GR64RegClass); in X86TargetLowering()
179 for (MVT VT : MVT::integer_valuetypes()) in X86TargetLowering()
180 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in X86TargetLowering()
183 setTruncStoreAction(MVT::i64, MVT::i32, Expand); in X86TargetLowering()
184 setTruncStoreAction(MVT::i64, MVT::i16, Expand); in X86TargetLowering()
185 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); in X86TargetLowering()
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Support/
HDMachineValueType.h30 class MVT {
267 constexpr MVT() = default;
268 constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {} in MVT() function
270 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
271 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
272 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
273 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
274 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
275 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
279 return (SimpleTy >= MVT::FIRST_VALUETYPE && in isValid()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMTargetTransformInfo.cpp161 { ISD::FP_ROUND, MVT::v2f64, 2 }, in getCastInstrCost()
162 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
163 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
168 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); in getCastInstrCost()
182 {ISD::SIGN_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
183 {ISD::ZERO_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
184 {ISD::SIGN_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
185 {ISD::ZERO_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
186 {ISD::SIGN_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
187 {ISD::ZERO_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
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HDARMCallingConv.h20 bool CC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
23 bool CC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT,
26 bool CC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
29 bool CC_ARM_APCS_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
32 bool FastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
35 bool CC_ARM_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT, MVT LocVT,
38 bool RetCC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
41 bool RetCC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT,
44 bool RetCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
47 bool RetFastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDValueTypes.cpp126 case MVT::ppcf128: return "ppcf128"; in getEVTString()
127 case MVT::isVoid: return "isVoid"; in getEVTString()
128 case MVT::Other: return "ch"; in getEVTString()
129 case MVT::Glue: return "glue"; in getEVTString()
130 case MVT::x86mmx: return "x86mmx"; in getEVTString()
131 case MVT::Metadata:return "Metadata"; in getEVTString()
132 case MVT::Untyped: return "Untyped"; in getEVTString()
133 case MVT::exnref : return "exnref"; in getEVTString()
145 case MVT::isVoid: return Type::getVoidTy(Context); in getTypeForEVT()
146 case MVT::i1: return Type::getInt1Ty(Context); in getTypeForEVT()
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HDTargetLoweringBase.cpp221 if (OpVT == MVT::f16) { in getFPEXT()
222 if (RetVT == MVT::f32) in getFPEXT()
224 } else if (OpVT == MVT::f32) { in getFPEXT()
225 if (RetVT == MVT::f64) in getFPEXT()
227 if (RetVT == MVT::f128) in getFPEXT()
229 if (RetVT == MVT::ppcf128) in getFPEXT()
231 } else if (OpVT == MVT::f64) { in getFPEXT()
232 if (RetVT == MVT::f128) in getFPEXT()
234 else if (RetVT == MVT::ppcf128) in getFPEXT()
236 } else if (OpVT == MVT::f80) { in getFPEXT()
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/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
HDCodeGenTarget.cpp45 MVT::SimpleValueType llvm::getValueType(Record *Rec) { in getValueType()
46 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); in getValueType()
49 StringRef llvm::getName(MVT::SimpleValueType T) { in getName()
51 case MVT::Other: return "UNKNOWN"; in getName()
52 case MVT::iPTR: return "TLI.getPointerTy()"; in getName()
53 case MVT::iPTRAny: return "TLI.getPointerTy()"; in getName()
58 StringRef llvm::getEnumName(MVT::SimpleValueType T) { in getEnumName()
60 case MVT::Other: return "MVT::Other"; in getEnumName()
61 case MVT::i1: return "MVT::i1"; in getEnumName()
62 case MVT::i8: return "MVT::i8"; in getEnumName()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64TargetTransformInfo.cpp302 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, in getCastInstrCost()
303 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
304 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
305 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
308 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
309 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
310 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
311 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
312 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
313 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
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HDAArch64ISelDAGToDAG.cpp162 template<MVT::SimpleValueType VT>
167 template<MVT::SimpleValueType VT>
187 Imm = CurDAG->getTargetConstant(MulImm, SDLoc(N), MVT::i32); in SelectCntImm()
271 bool SelectSVEAddSubImm(SDValue N, MVT VT, SDValue &Imm, SDValue &Shift);
273 bool SelectSVELogicalImm(SDValue N, MVT VT, SDValue &Imm);
318 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64); in SelectInlineAsmMemoryOperand()
355 Val = CurDAG->getTargetConstant(Immed, dl, MVT::i32); in SelectArithImmed()
356 Shift = CurDAG->getTargetConstant(ShVal, dl, MVT::i32); in SelectArithImmed()
381 if (N.getValueType() == MVT::i32) in SelectNegArithImmed()
389 return SelectArithImmed(CurDAG->getConstant(Immed, SDLoc(N), MVT::i32), Val, in SelectNegArithImmed()
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HDAArch64CallingConvention.h19 bool CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
22 bool CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
25 bool CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
28 bool CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
31 bool CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
34 bool CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT, MVT LocVT,
37 bool CC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, MVT LocVT,
40 bool CC_AArch64_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
43 bool RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
46 bool RetCC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, MVT LocVT,
HDAArch64FastISel.cpp182 bool isTypeLegal(Type *Ty, MVT &VT);
183 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
187 bool simplifyAddress(Address &Addr, MVT VT);
196 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
201 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
204 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
207 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
210 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
215 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
224 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
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HDAArch64ISelLowering.cpp122 static const MVT MVT_CC = MVT::i32;
135 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass); in AArch64TargetLowering()
136 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass); in AArch64TargetLowering()
139 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
140 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass); in AArch64TargetLowering()
141 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass); in AArch64TargetLowering()
142 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass); in AArch64TargetLowering()
146 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass); in AArch64TargetLowering()
147 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
149 addDRTypeForNEON(MVT::v2f32); in AArch64TargetLowering()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonISelLoweringHVX.cpp16 static const MVT LegalV64[] = { MVT::v64i8, MVT::v32i16, MVT::v16i32 };
17 static const MVT LegalW64[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
18 static const MVT LegalV128[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
19 static const MVT LegalW128[] = { MVT::v256i8, MVT::v128i16, MVT::v64i32 };
25 addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
26 addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
27 addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
28 addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
29 addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
30 addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
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HDHexagonISelLowering.cpp132 static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in CC_SkipOdd()
169 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); in CreateCopyOfByValArgument()
231 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps); in LowerReturn()
337 if (RVLocs[i].getValVT() == MVT::i1) { in LowerCallResult()
345 MVT::i32, Glue); in LowerCallResult()
354 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1); in LowerCallResult()
394 Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32); in LowerCall()
467 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr); in LowerCall()
500 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall()
552 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.cpp48 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); in getEquivalentMemType()
70 setOperationAction(ISD::LOAD, MVT::f32, Promote); in AMDGPUTargetLowering()
71 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
73 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); in AMDGPUTargetLowering()
74 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
76 setOperationAction(ISD::LOAD, MVT::v3f32, Promote); in AMDGPUTargetLowering()
77 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
79 setOperationAction(ISD::LOAD, MVT::v4f32, Promote); in AMDGPUTargetLowering()
80 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
82 setOperationAction(ISD::LOAD, MVT::v5f32, Promote); in AMDGPUTargetLowering()
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HDR600ISelLowering.cpp59 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
60 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
61 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
62 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
63 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
64 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
72 setOperationAction(ISD::LOAD, MVT::i32, Custom); in R600TargetLowering()
73 setOperationAction(ISD::LOAD, MVT::v2i32, Custom); in R600TargetLowering()
74 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); in R600TargetLowering()
78 for (MVT VT : MVT::integer_valuetypes()) { in R600TargetLowering()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp41 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_SRet()
42 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_SRet()
54 static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_Split_64()
55 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_Split_64()
82 static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_Ret_Split_64()
83 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_Ret_Split_64()
106 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, in CC_Sparc64_Full()
107 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc64_Full()
109 assert((LocVT == MVT::f32 || LocVT == MVT::f128 in CC_Sparc64_Full()
114 unsigned size = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
HDWebAssemblyFastISel.cpp117 MVT::SimpleValueType getSimpleType(Type *Ty) { in getSimpleType()
120 : MVT::INVALID_SIMPLE_VALUE_TYPE; in getSimpleType()
122 MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) { in getLegalType()
124 case MVT::i1: in getLegalType()
125 case MVT::i8: in getLegalType()
126 case MVT::i16: in getLegalType()
127 return MVT::i32; in getLegalType()
128 case MVT::i32: in getLegalType()
129 case MVT::i64: in getLegalType()
130 case MVT::f32: in getLegalType()
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HDWebAssemblyISelLowering.cpp43 auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32; in WebAssemblyTargetLowering()
55 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass); in WebAssemblyTargetLowering()
56 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass); in WebAssemblyTargetLowering()
57 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass); in WebAssemblyTargetLowering()
58 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass); in WebAssemblyTargetLowering()
60 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
61 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
62 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
63 addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
66 addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp146 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
149 addRegisterClass(MVT::f32, &PPC::GPRCRegClass); in PPCTargetLowering()
150 addRegisterClass(MVT::f64, &PPC::SPERCRegClass); in PPCTargetLowering()
152 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
153 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
158 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in PPCTargetLowering()
159 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in PPCTargetLowering()
162 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); in PPCTargetLowering()
165 for (MVT VT : MVT::integer_valuetypes()) { in PPCTargetLowering()
166 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
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HDPPCFastISel.cpp113 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
145 bool isTypeLegal(Type *Ty, MVT &VT);
146 bool isLoadTypeLegal(Type *Ty, MVT &VT);
165 bool PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
168 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
172 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
174 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
175 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
176 unsigned PPCMaterializeInt(const ConstantInt *CI, MVT VT,
182 unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsFastISel.cpp172 bool isTypeLegal(Type *Ty, MVT &VT);
173 bool isTypeSupported(Type *Ty, MVT &VT);
174 bool isLoadTypeLegal(Type *Ty, MVT &VT);
181 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
183 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
185 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
187 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
188 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
191 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
193 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
HDXCoreISelLowering.cpp78 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); in XCoreTargetLowering()
92 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in XCoreTargetLowering()
93 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in XCoreTargetLowering()
96 setOperationAction(ISD::ADD, MVT::i64, Custom); in XCoreTargetLowering()
97 setOperationAction(ISD::SUB, MVT::i64, Custom); in XCoreTargetLowering()
98 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); in XCoreTargetLowering()
99 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom); in XCoreTargetLowering()
100 setOperationAction(ISD::MULHS, MVT::i32, Expand); in XCoreTargetLowering()
101 setOperationAction(ISD::MULHU, MVT::i32, Expand); in XCoreTargetLowering()
102 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); in XCoreTargetLowering()
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDValueTypes.h36 MVT V = MVT::INVALID_SIMPLE_VALUE_TYPE;
41 constexpr EVT(MVT::SimpleValueType SVT) : V(SVT) {} in EVT()
42 constexpr EVT(MVT S) : V(S) {} in EVT()
50 if (V.SimpleTy == MVT::INVALID_SIMPLE_VALUE_TYPE)
59 return MVT::getFloatingPointVT(BitWidth); in getFloatingPointVT()
65 MVT M = MVT::getIntegerVT(BitWidth); in getIntegerVT()
66 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE) in getIntegerVT()
75 MVT M = MVT::getVectorVT(VT.V, NumElements, IsScalable);
76 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE)
86 MVT M = MVT::getVectorVT(VT.V, EC); in getVectorVT()
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