1 /*-
2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD$
26 */
27
28 #ifndef MLX5_DRIVER_H
29 #define MLX5_DRIVER_H
30
31 #include <linux/kernel.h>
32 #include <linux/completion.h>
33 #include <linux/pci.h>
34 #include <linux/cache.h>
35 #include <linux/rbtree.h>
36 #include <linux/if_ether.h>
37 #include <linux/semaphore.h>
38 #include <linux/slab.h>
39 #include <linux/vmalloc.h>
40 #include <linux/radix-tree.h>
41 #include <linux/idr.h>
42 #include <linux/wait.h>
43
44 #include <dev/mlx5/device.h>
45 #include <dev/mlx5/doorbell.h>
46 #include <dev/mlx5/srq.h>
47
48 #define MLX5_QCOUNTER_SETS_NETDEV 64
49 #define MLX5_MAX_NUMBER_OF_VFS 128
50
51 enum {
52 MLX5_BOARD_ID_LEN = 64,
53 MLX5_MAX_NAME_LEN = 16,
54 };
55
56 enum {
57 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
58 };
59
60 enum {
61 CMD_OWNER_SW = 0x0,
62 CMD_OWNER_HW = 0x1,
63 CMD_STATUS_SUCCESS = 0,
64 };
65
66 enum mlx5_sqp_t {
67 MLX5_SQP_SMI = 0,
68 MLX5_SQP_GSI = 1,
69 MLX5_SQP_IEEE_1588 = 2,
70 MLX5_SQP_SNIFFER = 3,
71 MLX5_SQP_SYNC_UMR = 4,
72 };
73
74 enum {
75 MLX5_MAX_PORTS = 2,
76 };
77
78 enum {
79 MLX5_EQ_VEC_PAGES = 0,
80 MLX5_EQ_VEC_CMD = 1,
81 MLX5_EQ_VEC_ASYNC = 2,
82 MLX5_EQ_VEC_COMP_BASE,
83 };
84
85 enum {
86 MLX5_ATOMIC_MODE_OFF = 16,
87 MLX5_ATOMIC_MODE_NONE = 0 << MLX5_ATOMIC_MODE_OFF,
88 MLX5_ATOMIC_MODE_IB_COMP = 1 << MLX5_ATOMIC_MODE_OFF,
89 MLX5_ATOMIC_MODE_CX = 2 << MLX5_ATOMIC_MODE_OFF,
90 MLX5_ATOMIC_MODE_8B = 3 << MLX5_ATOMIC_MODE_OFF,
91 MLX5_ATOMIC_MODE_16B = 4 << MLX5_ATOMIC_MODE_OFF,
92 MLX5_ATOMIC_MODE_32B = 5 << MLX5_ATOMIC_MODE_OFF,
93 MLX5_ATOMIC_MODE_64B = 6 << MLX5_ATOMIC_MODE_OFF,
94 MLX5_ATOMIC_MODE_128B = 7 << MLX5_ATOMIC_MODE_OFF,
95 MLX5_ATOMIC_MODE_256B = 8 << MLX5_ATOMIC_MODE_OFF,
96 };
97
98 enum {
99 MLX5_ATOMIC_MODE_DCT_OFF = 20,
100 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF,
101 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF,
102 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF,
103 MLX5_ATOMIC_MODE_DCT_8B = 3 << MLX5_ATOMIC_MODE_DCT_OFF,
104 MLX5_ATOMIC_MODE_DCT_16B = 4 << MLX5_ATOMIC_MODE_DCT_OFF,
105 MLX5_ATOMIC_MODE_DCT_32B = 5 << MLX5_ATOMIC_MODE_DCT_OFF,
106 MLX5_ATOMIC_MODE_DCT_64B = 6 << MLX5_ATOMIC_MODE_DCT_OFF,
107 MLX5_ATOMIC_MODE_DCT_128B = 7 << MLX5_ATOMIC_MODE_DCT_OFF,
108 MLX5_ATOMIC_MODE_DCT_256B = 8 << MLX5_ATOMIC_MODE_DCT_OFF,
109 };
110
111 enum {
112 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
113 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
114 MLX5_ATOMIC_OPS_MASKED_CMP_SWAP = 1 << 2,
115 MLX5_ATOMIC_OPS_MASKED_FETCH_ADD = 1 << 3,
116 };
117
118 enum {
119 MLX5_REG_QPTS = 0x4002,
120 MLX5_REG_QETCR = 0x4005,
121 MLX5_REG_QPDP = 0x4007,
122 MLX5_REG_QTCT = 0x400A,
123 MLX5_REG_QPDPM = 0x4013,
124 MLX5_REG_QHLL = 0x4016,
125 MLX5_REG_QCAM = 0x4019,
126 MLX5_REG_DCBX_PARAM = 0x4020,
127 MLX5_REG_DCBX_APP = 0x4021,
128 MLX5_REG_FPGA_CAP = 0x4022,
129 MLX5_REG_FPGA_CTRL = 0x4023,
130 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
131 MLX5_REG_FPGA_SHELL_CNTR = 0x4025,
132 MLX5_REG_PCAP = 0x5001,
133 MLX5_REG_PMLP = 0x5002,
134 MLX5_REG_PMTU = 0x5003,
135 MLX5_REG_PTYS = 0x5004,
136 MLX5_REG_PAOS = 0x5006,
137 MLX5_REG_PFCC = 0x5007,
138 MLX5_REG_PPCNT = 0x5008,
139 MLX5_REG_PUDE = 0x5009,
140 MLX5_REG_PPTB = 0x500B,
141 MLX5_REG_PBMC = 0x500C,
142 MLX5_REG_PELC = 0x500E,
143 MLX5_REG_PVLC = 0x500F,
144 MLX5_REG_PMPE = 0x5010,
145 MLX5_REG_PMAOS = 0x5012,
146 MLX5_REG_PPLM = 0x5023,
147 MLX5_REG_PDDR = 0x5031,
148 MLX5_REG_PBSR = 0x5038,
149 MLX5_REG_PCAM = 0x507f,
150 MLX5_REG_NODE_DESC = 0x6001,
151 MLX5_REG_HOST_ENDIANNESS = 0x7004,
152 MLX5_REG_MTMP = 0x900a,
153 MLX5_REG_MCIA = 0x9014,
154 MLX5_REG_MFRL = 0x9028,
155 MLX5_REG_MPCNT = 0x9051,
156 MLX5_REG_MCQI = 0x9061,
157 MLX5_REG_MCC = 0x9062,
158 MLX5_REG_MCDA = 0x9063,
159 MLX5_REG_MCAM = 0x907f,
160 };
161
162 enum dbg_rsc_type {
163 MLX5_DBG_RSC_QP,
164 MLX5_DBG_RSC_EQ,
165 MLX5_DBG_RSC_CQ,
166 };
167
168 enum {
169 MLX5_INTERFACE_PROTOCOL_IB = 0,
170 MLX5_INTERFACE_PROTOCOL_ETH = 1,
171 MLX5_INTERFACE_NUMBER = 2,
172 };
173
174 struct mlx5_field_desc {
175 struct dentry *dent;
176 int i;
177 };
178
179 struct mlx5_rsc_debug {
180 struct mlx5_core_dev *dev;
181 void *object;
182 enum dbg_rsc_type type;
183 struct dentry *root;
184 struct mlx5_field_desc fields[0];
185 };
186
187 enum mlx5_dev_event {
188 MLX5_DEV_EVENT_SYS_ERROR,
189 MLX5_DEV_EVENT_PORT_UP,
190 MLX5_DEV_EVENT_PORT_DOWN,
191 MLX5_DEV_EVENT_PORT_INITIALIZED,
192 MLX5_DEV_EVENT_LID_CHANGE,
193 MLX5_DEV_EVENT_PKEY_CHANGE,
194 MLX5_DEV_EVENT_GUID_CHANGE,
195 MLX5_DEV_EVENT_CLIENT_REREG,
196 MLX5_DEV_EVENT_VPORT_CHANGE,
197 MLX5_DEV_EVENT_ERROR_STATE_DCBX,
198 MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE,
199 MLX5_DEV_EVENT_LOCAL_OPER_CHANGE,
200 MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE,
201 };
202
203 enum mlx5_port_status {
204 MLX5_PORT_UP = 1 << 0,
205 MLX5_PORT_DOWN = 1 << 1,
206 };
207
208 enum {
209 MLX5_VSC_SPACE_SUPPORTED = 0x1,
210 MLX5_VSC_SPACE_OFFSET = 0x4,
211 MLX5_VSC_COUNTER_OFFSET = 0x8,
212 MLX5_VSC_SEMA_OFFSET = 0xC,
213 MLX5_VSC_ADDR_OFFSET = 0x10,
214 MLX5_VSC_DATA_OFFSET = 0x14,
215 MLX5_VSC_MAX_RETRIES = 0x1000,
216 };
217
218 #define MLX5_PROT_MASK(link_mode) (1 << link_mode)
219
220 struct mlx5_uuar_info {
221 struct mlx5_uar *uars;
222 int num_uars;
223 int num_low_latency_uuars;
224 unsigned long *bitmap;
225 unsigned int *count;
226 struct mlx5_bf *bfs;
227
228 /*
229 * protect uuar allocation data structs
230 */
231 struct mutex lock;
232 u32 ver;
233 };
234
235 struct mlx5_bf {
236 void __iomem *reg;
237 void __iomem *regreg;
238 int buf_size;
239 struct mlx5_uar *uar;
240 unsigned long offset;
241 int need_lock;
242 /* protect blue flame buffer selection when needed
243 */
244 spinlock_t lock;
245
246 /* serialize 64 bit writes when done as two 32 bit accesses
247 */
248 spinlock_t lock32;
249 int uuarn;
250 };
251
252 struct mlx5_cmd_first {
253 __be32 data[4];
254 };
255
256 struct cache_ent;
257 struct mlx5_fw_page {
258 union {
259 struct rb_node rb_node;
260 struct list_head list;
261 };
262 struct mlx5_cmd_first first;
263 struct mlx5_core_dev *dev;
264 bus_dmamap_t dma_map;
265 bus_addr_t dma_addr;
266 void *virt_addr;
267 struct cache_ent *cache;
268 u32 numpages;
269 u16 load_done;
270 #define MLX5_LOAD_ST_NONE 0
271 #define MLX5_LOAD_ST_SUCCESS 1
272 #define MLX5_LOAD_ST_FAILURE 2
273 u16 func_id;
274 };
275 #define mlx5_cmd_msg mlx5_fw_page
276
277 struct mlx5_cmd_debug {
278 struct dentry *dbg_root;
279 struct dentry *dbg_in;
280 struct dentry *dbg_out;
281 struct dentry *dbg_outlen;
282 struct dentry *dbg_status;
283 struct dentry *dbg_run;
284 void *in_msg;
285 void *out_msg;
286 u8 status;
287 u16 inlen;
288 u16 outlen;
289 };
290
291 struct cache_ent {
292 /* protect block chain allocations
293 */
294 spinlock_t lock;
295 struct list_head head;
296 };
297
298 struct cmd_msg_cache {
299 struct cache_ent large;
300 struct cache_ent med;
301
302 };
303
304 struct mlx5_traffic_counter {
305 u64 packets;
306 u64 octets;
307 };
308
309 enum mlx5_cmd_mode {
310 MLX5_CMD_MODE_POLLING,
311 MLX5_CMD_MODE_EVENTS
312 };
313
314 struct mlx5_cmd_stats {
315 u64 sum;
316 u64 n;
317 struct dentry *root;
318 struct dentry *avg;
319 struct dentry *count;
320 /* protect command average calculations */
321 spinlock_t lock;
322 };
323
324 struct mlx5_cmd {
325 struct mlx5_fw_page *cmd_page;
326 bus_dma_tag_t dma_tag;
327 struct sx dma_sx;
328 struct mtx dma_mtx;
329 #define MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx)
330 #define MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx)
331 #define MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx)
332 struct cv dma_cv;
333 #define MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv)
334 #define MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx)
335 void *cmd_buf;
336 dma_addr_t dma;
337 u16 cmdif_rev;
338 u8 log_sz;
339 u8 log_stride;
340 int max_reg_cmds;
341 int events;
342 u32 __iomem *vector;
343
344 /* protect command queue allocations
345 */
346 spinlock_t alloc_lock;
347
348 /* protect token allocations
349 */
350 spinlock_t token_lock;
351 u8 token;
352 unsigned long bitmask;
353 struct semaphore sem;
354 struct semaphore pages_sem;
355 enum mlx5_cmd_mode mode;
356 struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS];
357 volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS];
358 struct mlx5_cmd_debug dbg;
359 struct cmd_msg_cache cache;
360 int checksum_disabled;
361 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
362 };
363
364 struct mlx5_port_caps {
365 int gid_table_len;
366 int pkey_table_len;
367 u8 ext_port_cap;
368 };
369
370 struct mlx5_buf {
371 bus_dma_tag_t dma_tag;
372 bus_dmamap_t dma_map;
373 struct mlx5_core_dev *dev;
374 struct {
375 void *buf;
376 } direct;
377 u64 *page_list;
378 int npages;
379 int size;
380 u8 page_shift;
381 u8 load_done;
382 };
383
384 struct mlx5_frag_buf {
385 struct mlx5_buf_list *frags;
386 int npages;
387 int size;
388 u8 page_shift;
389 };
390
391 struct mlx5_eq {
392 struct mlx5_core_dev *dev;
393 __be32 __iomem *doorbell;
394 u32 cons_index;
395 struct mlx5_buf buf;
396 int size;
397 u8 irqn;
398 u8 eqn;
399 int nent;
400 u64 mask;
401 struct list_head list;
402 int index;
403 struct mlx5_rsc_debug *dbg;
404 };
405
406 struct mlx5_core_psv {
407 u32 psv_idx;
408 struct psv_layout {
409 u32 pd;
410 u16 syndrome;
411 u16 reserved;
412 u16 bg;
413 u16 app_tag;
414 u32 ref_tag;
415 } psv;
416 };
417
418 struct mlx5_core_sig_ctx {
419 struct mlx5_core_psv psv_memory;
420 struct mlx5_core_psv psv_wire;
421 #if (__FreeBSD_version >= 1100000)
422 struct ib_sig_err err_item;
423 #endif
424 bool sig_status_checked;
425 bool sig_err_exists;
426 u32 sigerr_count;
427 };
428
429 enum {
430 MLX5_MKEY_MR = 1,
431 MLX5_MKEY_MW,
432 MLX5_MKEY_MR_USER,
433 };
434
435 struct mlx5_core_mkey {
436 u64 iova;
437 u64 size;
438 u32 key;
439 u32 pd;
440 u32 type;
441 };
442
443 struct mlx5_core_mr {
444 u64 iova;
445 u64 size;
446 u32 key;
447 u32 pd;
448 };
449
450 enum mlx5_res_type {
451 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
452 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
453 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
454 MLX5_RES_SRQ = 3,
455 MLX5_RES_XSRQ = 4,
456 MLX5_RES_DCT = 5,
457 };
458
459 struct mlx5_core_rsc_common {
460 enum mlx5_res_type res;
461 atomic_t refcount;
462 struct completion free;
463 };
464
465 struct mlx5_core_srq {
466 struct mlx5_core_rsc_common common; /* must be first */
467 u32 srqn;
468 int max;
469 size_t max_gs;
470 size_t max_avail_gather;
471 int wqe_shift;
472 void (*event)(struct mlx5_core_srq *, int);
473 atomic_t refcount;
474 struct completion free;
475 };
476
477 struct mlx5_eq_table {
478 void __iomem *update_ci;
479 void __iomem *update_arm_ci;
480 struct list_head comp_eqs_list;
481 struct mlx5_eq pages_eq;
482 struct mlx5_eq async_eq;
483 struct mlx5_eq cmd_eq;
484 int num_comp_vectors;
485 /* protect EQs list
486 */
487 spinlock_t lock;
488 };
489
490 struct mlx5_uar {
491 u32 index;
492 void __iomem *bf_map;
493 void __iomem *map;
494 };
495
496
497 struct mlx5_core_health {
498 struct mlx5_health_buffer __iomem *health;
499 __be32 __iomem *health_counter;
500 struct timer_list timer;
501 u32 prev;
502 int miss_counter;
503 u32 fatal_error;
504 struct workqueue_struct *wq_watchdog;
505 struct work_struct work_watchdog;
506 /* wq spinlock to synchronize draining */
507 spinlock_t wq_lock;
508 struct workqueue_struct *wq;
509 unsigned long flags;
510 struct work_struct work;
511 struct delayed_work recover_work;
512 unsigned int last_reset_req;
513 struct work_struct work_cmd_completion;
514 struct workqueue_struct *wq_cmd;
515 };
516
517 #define MLX5_CQ_LINEAR_ARRAY_SIZE 1024
518
519 struct mlx5_cq_linear_array_entry {
520 spinlock_t lock;
521 struct mlx5_core_cq * volatile cq;
522 };
523
524 struct mlx5_cq_table {
525 /* protect radix tree
526 */
527 spinlock_t lock;
528 struct radix_tree_root tree;
529 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE];
530 };
531
532 struct mlx5_qp_table {
533 /* protect radix tree
534 */
535 spinlock_t lock;
536 struct radix_tree_root tree;
537 };
538
539 struct mlx5_srq_table {
540 /* protect radix tree
541 */
542 spinlock_t lock;
543 struct radix_tree_root tree;
544 };
545
546 struct mlx5_mr_table {
547 /* protect radix tree
548 */
549 spinlock_t lock;
550 struct radix_tree_root tree;
551 };
552
553 struct mlx5_pme_stats {
554 u64 status_counters[MLX5_MODULE_STATUS_NUM];
555 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
556 };
557
558 struct mlx5_priv {
559 char name[MLX5_MAX_NAME_LEN];
560 struct mlx5_eq_table eq_table;
561 struct msix_entry *msix_arr;
562 struct mlx5_uuar_info uuari;
563 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
564 int disable_irqs;
565
566 struct io_mapping *bf_mapping;
567
568 /* pages stuff */
569 struct workqueue_struct *pg_wq;
570 struct rb_root page_root;
571 s64 fw_pages;
572 atomic_t reg_pages;
573 s64 pages_per_func[MLX5_MAX_NUMBER_OF_VFS];
574 struct mlx5_core_health health;
575
576 struct mlx5_srq_table srq_table;
577
578 /* start: qp staff */
579 struct mlx5_qp_table qp_table;
580 struct dentry *qp_debugfs;
581 struct dentry *eq_debugfs;
582 struct dentry *cq_debugfs;
583 struct dentry *cmdif_debugfs;
584 /* end: qp staff */
585
586 /* start: cq staff */
587 struct mlx5_cq_table cq_table;
588 /* end: cq staff */
589
590 /* start: mr staff */
591 struct mlx5_mr_table mr_table;
592 /* end: mr staff */
593
594 /* start: alloc staff */
595 int numa_node;
596
597 struct mutex pgdir_mutex;
598 struct list_head pgdir_list;
599 /* end: alloc staff */
600 struct dentry *dbg_root;
601
602 /* protect mkey key part */
603 spinlock_t mkey_lock;
604 u8 mkey_key;
605
606 struct list_head dev_list;
607 struct list_head ctx_list;
608 spinlock_t ctx_lock;
609 unsigned long pci_dev_data;
610 struct mlx5_pme_stats pme_stats;
611
612 struct mlx5_eswitch *eswitch;
613 };
614
615 enum mlx5_device_state {
616 MLX5_DEVICE_STATE_UP,
617 MLX5_DEVICE_STATE_INTERNAL_ERROR,
618 };
619
620 enum mlx5_interface_state {
621 MLX5_INTERFACE_STATE_UP = 0x1,
622 MLX5_INTERFACE_STATE_TEARDOWN = 0x2,
623 };
624
625 enum mlx5_pci_status {
626 MLX5_PCI_STATUS_DISABLED,
627 MLX5_PCI_STATUS_ENABLED,
628 };
629
630 #define MLX5_MAX_RESERVED_GIDS 8
631
632 struct mlx5_rsvd_gids {
633 unsigned int start;
634 unsigned int count;
635 struct ida ida;
636 };
637
638 struct mlx5_special_contexts {
639 int resd_lkey;
640 };
641
642 struct mlx5_flow_root_namespace;
643 struct mlx5_core_dev {
644 struct pci_dev *pdev;
645 /* sync pci state */
646 struct mutex pci_status_mutex;
647 enum mlx5_pci_status pci_status;
648 char board_id[MLX5_BOARD_ID_LEN];
649 struct mlx5_cmd cmd;
650 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
651 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
652 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
653 struct {
654 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
655 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
656 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
657 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
658 } caps;
659 phys_addr_t iseg_base;
660 struct mlx5_init_seg __iomem *iseg;
661 enum mlx5_device_state state;
662 /* sync interface state */
663 struct mutex intf_state_mutex;
664 unsigned long intf_state;
665 void (*event) (struct mlx5_core_dev *dev,
666 enum mlx5_dev_event event,
667 unsigned long param);
668 struct mlx5_priv priv;
669 struct mlx5_profile *profile;
670 atomic_t num_qps;
671 u32 vsc_addr;
672 u32 issi;
673 struct mlx5_special_contexts special_contexts;
674 unsigned int module_status[MLX5_MAX_PORTS];
675 struct mlx5_flow_root_namespace *root_ns;
676 struct mlx5_flow_root_namespace *fdb_root_ns;
677 struct mlx5_flow_root_namespace *esw_egress_root_ns;
678 struct mlx5_flow_root_namespace *esw_ingress_root_ns;
679 struct mlx5_flow_root_namespace *sniffer_rx_root_ns;
680 struct mlx5_flow_root_namespace *sniffer_tx_root_ns;
681 u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER];
682 struct mlx5_crspace_regmap *dump_rege;
683 uint32_t *dump_data;
684 unsigned dump_size;
685 bool dump_valid;
686 bool dump_copyout;
687 struct mtx dump_lock;
688
689 struct sysctl_ctx_list sysctl_ctx;
690 int msix_eqvec;
691 int pwr_status;
692 int pwr_value;
693
694 struct {
695 struct mlx5_rsvd_gids reserved_gids;
696 atomic_t roce_en;
697 } roce;
698
699 struct {
700 spinlock_t spinlock;
701 #define MLX5_MPFS_TABLE_MAX 32
702 long bitmap[BITS_TO_LONGS(MLX5_MPFS_TABLE_MAX)];
703 } mpfs;
704 #ifdef CONFIG_MLX5_FPGA
705 struct mlx5_fpga_device *fpga;
706 #endif
707 };
708
709 enum {
710 MLX5_WOL_DISABLE = 0,
711 MLX5_WOL_SECURED_MAGIC = 1 << 1,
712 MLX5_WOL_MAGIC = 1 << 2,
713 MLX5_WOL_ARP = 1 << 3,
714 MLX5_WOL_BROADCAST = 1 << 4,
715 MLX5_WOL_MULTICAST = 1 << 5,
716 MLX5_WOL_UNICAST = 1 << 6,
717 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
718 };
719
720 struct mlx5_db {
721 __be32 *db;
722 union {
723 struct mlx5_db_pgdir *pgdir;
724 struct mlx5_ib_user_db_page *user_page;
725 } u;
726 dma_addr_t dma;
727 int index;
728 };
729
730 struct mlx5_net_counters {
731 u64 packets;
732 u64 octets;
733 };
734
735 struct mlx5_ptys_reg {
736 u8 an_dis_admin;
737 u8 an_dis_ap;
738 u8 local_port;
739 u8 proto_mask;
740 u32 eth_proto_cap;
741 u16 ib_link_width_cap;
742 u16 ib_proto_cap;
743 u32 eth_proto_admin;
744 u16 ib_link_width_admin;
745 u16 ib_proto_admin;
746 u32 eth_proto_oper;
747 u16 ib_link_width_oper;
748 u16 ib_proto_oper;
749 u32 eth_proto_lp_advertise;
750 };
751
752 struct mlx5_pvlc_reg {
753 u8 local_port;
754 u8 vl_hw_cap;
755 u8 vl_admin;
756 u8 vl_operational;
757 };
758
759 struct mlx5_pmtu_reg {
760 u8 local_port;
761 u16 max_mtu;
762 u16 admin_mtu;
763 u16 oper_mtu;
764 };
765
766 struct mlx5_vport_counters {
767 struct mlx5_net_counters received_errors;
768 struct mlx5_net_counters transmit_errors;
769 struct mlx5_net_counters received_ib_unicast;
770 struct mlx5_net_counters transmitted_ib_unicast;
771 struct mlx5_net_counters received_ib_multicast;
772 struct mlx5_net_counters transmitted_ib_multicast;
773 struct mlx5_net_counters received_eth_broadcast;
774 struct mlx5_net_counters transmitted_eth_broadcast;
775 struct mlx5_net_counters received_eth_unicast;
776 struct mlx5_net_counters transmitted_eth_unicast;
777 struct mlx5_net_counters received_eth_multicast;
778 struct mlx5_net_counters transmitted_eth_multicast;
779 };
780
781 enum {
782 MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES,
783 };
784
785 struct mlx5_core_dct {
786 struct mlx5_core_rsc_common common; /* must be first */
787 void (*event)(struct mlx5_core_dct *, int);
788 int dctn;
789 struct completion drained;
790 struct mlx5_rsc_debug *dbg;
791 int pid;
792 };
793
794 enum {
795 MLX5_COMP_EQ_SIZE = 1024,
796 };
797
798 enum {
799 MLX5_PTYS_IB = 1 << 0,
800 MLX5_PTYS_EN = 1 << 2,
801 };
802
803 struct mlx5_db_pgdir {
804 struct list_head list;
805 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
806 struct mlx5_fw_page *fw_page;
807 __be32 *db_page;
808 dma_addr_t db_dma;
809 };
810
811 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
812
813 struct mlx5_cmd_work_ent {
814 struct mlx5_cmd_msg *in;
815 struct mlx5_cmd_msg *out;
816 int uin_size;
817 void *uout;
818 int uout_size;
819 mlx5_cmd_cbk_t callback;
820 struct delayed_work cb_timeout_work;
821 void *context;
822 int idx;
823 struct completion done;
824 struct mlx5_cmd *cmd;
825 struct work_struct work;
826 struct mlx5_cmd_layout *lay;
827 int ret;
828 int page_queue;
829 u8 status;
830 u8 token;
831 u64 ts1;
832 u64 ts2;
833 u16 op;
834 u8 busy;
835 bool polling;
836 };
837
838 struct mlx5_pas {
839 u64 pa;
840 u8 log_sz;
841 };
842
843 enum port_state_policy {
844 MLX5_POLICY_DOWN = 0,
845 MLX5_POLICY_UP = 1,
846 MLX5_POLICY_FOLLOW = 2,
847 MLX5_POLICY_INVALID = 0xffffffff
848 };
849
850 static inline void *
mlx5_buf_offset(struct mlx5_buf * buf,int offset)851 mlx5_buf_offset(struct mlx5_buf *buf, int offset)
852 {
853 return ((char *)buf->direct.buf + offset);
854 }
855
856
857 extern struct workqueue_struct *mlx5_core_wq;
858
859 #define STRUCT_FIELD(header, field) \
860 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
861 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
862
pci2mlx5_core_dev(struct pci_dev * pdev)863 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
864 {
865 return pci_get_drvdata(pdev);
866 }
867
868 extern struct dentry *mlx5_debugfs_root;
869
fw_rev_maj(struct mlx5_core_dev * dev)870 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
871 {
872 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
873 }
874
fw_rev_min(struct mlx5_core_dev * dev)875 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
876 {
877 return ioread32be(&dev->iseg->fw_rev) >> 16;
878 }
879
fw_rev_sub(struct mlx5_core_dev * dev)880 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
881 {
882 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
883 }
884
cmdif_rev_get(struct mlx5_core_dev * dev)885 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev)
886 {
887 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
888 }
889
mlx5_get_gid_table_len(u16 param)890 static inline int mlx5_get_gid_table_len(u16 param)
891 {
892 if (param > 4) {
893 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n");
894 return 0;
895 }
896
897 return 8 * (1 << param);
898 }
899
mlx5_vzalloc(unsigned long size)900 static inline void *mlx5_vzalloc(unsigned long size)
901 {
902 void *rtn;
903
904 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
905 return rtn;
906 }
907
mlx5_vmalloc(unsigned long size)908 static inline void *mlx5_vmalloc(unsigned long size)
909 {
910 void *rtn;
911
912 rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);
913 if (!rtn)
914 rtn = vmalloc(size);
915 return rtn;
916 }
917
mlx5_base_mkey(const u32 key)918 static inline u32 mlx5_base_mkey(const u32 key)
919 {
920 return key & 0xffffff00u;
921 }
922
923 int mlx5_cmd_init(struct mlx5_core_dev *dev);
924 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
925 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
926 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
927 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
928 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
929
930 struct mlx5_async_ctx {
931 struct mlx5_core_dev *dev;
932 atomic_t num_inflight;
933 struct wait_queue_head wait;
934 };
935
936 struct mlx5_async_work;
937
938 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
939
940 struct mlx5_async_work {
941 struct mlx5_async_ctx *ctx;
942 mlx5_async_cbk_t user_callback;
943 };
944
945 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
946 struct mlx5_async_ctx *ctx);
947 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
948 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
949 void *out, int out_size, mlx5_async_cbk_t callback,
950 struct mlx5_async_work *work);
951 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
952 int out_size);
953 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
954 void *out, int out_size);
955 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
956 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
957 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
958 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
959 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
960 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
961 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
962 int mlx5_health_init(struct mlx5_core_dev *dev);
963 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
964 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
965 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
966 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
967 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
968 void mlx5_trigger_health_watchdog(struct mlx5_core_dev *dev);
969
970 #define mlx5_buf_alloc_node(dev, size, direct, buf, node) \
971 mlx5_buf_alloc(dev, size, direct, buf)
972 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
973 struct mlx5_buf *buf);
974 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
975 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
976 struct mlx5_srq_attr *in);
977 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
978 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
979 struct mlx5_srq_attr *out);
980 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
981 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
982 u16 lwm, int is_srq);
983 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
984 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
985 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
986 struct mlx5_core_mr *mkey,
987 struct mlx5_async_ctx *async_ctx, u32 *in,
988 int inlen, u32 *out, int outlen,
989 mlx5_async_cbk_t callback,
990 struct mlx5_async_work *context);
991 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
992 struct mlx5_core_mr *mr,
993 u32 *in, int inlen);
994 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey);
995 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey,
996 u32 *out, int outlen);
997 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
998 u32 *mkey);
999 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1000 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1001 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1002 u16 opmod, u8 port);
1003 void mlx5_fwp_flush(struct mlx5_fw_page *fwp);
1004 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp);
1005 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num);
1006 void mlx5_fwp_free(struct mlx5_fw_page *fwp);
1007 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset);
1008 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset);
1009 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1010 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1011 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1012 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1013 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1014 s32 npages);
1015 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1016 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1017 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev);
1018 void mlx5_register_debugfs(void);
1019 void mlx5_unregister_debugfs(void);
1020 int mlx5_eq_init(struct mlx5_core_dev *dev);
1021 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1022 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1023 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
1024 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1025 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1026 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1027 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode);
1028 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1029 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1030 int nent, u64 mask, struct mlx5_uar *uar);
1031 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1032 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1033 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1034 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
1035 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1036 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1037 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
1038 u64 addr);
1039
1040 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1041 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1042 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1043 int size_in, void *data_out, int size_out,
1044 u16 reg_num, int arg, int write);
1045
1046 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
1047
1048 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1049 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1050 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1051 u32 *out, int outlen);
1052 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1053 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1054 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1055 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1056 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1057 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1058 int node);
1059 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1060
1061 const char *mlx5_command_str(int command);
1062 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1063 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1064 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1065 int npsvs, u32 *sig_index);
1066 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1067 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1068 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev);
1069 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode);
1070 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout);
1071 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout);
1072 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode);
1073 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
1074 struct mlx5_pvlc_reg *pvlc, int write);
1075 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
1076 struct mlx5_ptys_reg *ptys, int write);
1077 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
1078 struct mlx5_pmtu_reg *pmtu, int write);
1079 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port);
1080 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port);
1081 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1082 int priority, int *is_enable);
1083 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1084 int priority, int enable);
1085 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
1086 void *out, int out_size);
1087 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
1088 void *in, int in_size);
1089 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
1090 void *out, int out_size);
1091 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
1092 int in_size);
1093 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
1094 u8 num_of_samples, u16 sample_index,
1095 void *out, int out_size);
1096 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev);
1097 int mlx5_vsc_lock(struct mlx5_core_dev *mdev);
1098 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev);
1099 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space);
1100 int mlx5_vsc_wait_on_flag(struct mlx5_core_dev *mdev, u32 expected);
1101 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data);
1102 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data);
1103 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1104 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1105 int mlx5_pci_read_power_status(struct mlx5_core_dev *mdev,
1106 u16 *p_power, u8 *p_status);
1107
mlx5_mkey_to_idx(u32 mkey)1108 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1109 {
1110 return mkey >> 8;
1111 }
1112
mlx5_idx_to_mkey(u32 mkey_idx)1113 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1114 {
1115 return mkey_idx << 8;
1116 }
1117
mlx5_mkey_variant(u32 mkey)1118 static inline u8 mlx5_mkey_variant(u32 mkey)
1119 {
1120 return mkey & 0xff;
1121 }
1122
1123 enum {
1124 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
1125 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
1126 };
1127
1128 enum {
1129 MAX_MR_CACHE_ENTRIES = 15,
1130 };
1131
1132 struct mlx5_interface {
1133 void * (*add)(struct mlx5_core_dev *dev);
1134 void (*remove)(struct mlx5_core_dev *dev, void *context);
1135 void (*event)(struct mlx5_core_dev *dev, void *context,
1136 enum mlx5_dev_event event, unsigned long param);
1137 void * (*get_dev)(void *context);
1138 int protocol;
1139 struct list_head list;
1140 };
1141
1142 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1143 int mlx5_register_interface(struct mlx5_interface *intf);
1144 void mlx5_unregister_interface(struct mlx5_interface *intf);
1145
1146 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1147 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1148 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1149 const u8 *mac, bool vlan, u16 vlan_id);
1150
1151 struct mlx5_profile {
1152 u64 mask;
1153 u8 log_max_qp;
1154 struct {
1155 int size;
1156 int limit;
1157 } mr_cache[MAX_MR_CACHE_ENTRIES];
1158 };
1159
1160 enum {
1161 MLX5_PCI_DEV_IS_VF = 1 << 0,
1162 };
1163
1164 enum {
1165 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1166 };
1167
mlx5_core_is_pf(struct mlx5_core_dev * dev)1168 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1169 {
1170 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1171 }
1172
1173 void mlx5_disable_interrupts(struct mlx5_core_dev *);
1174 void mlx5_poll_interrupts(struct mlx5_core_dev *);
1175
1176 #endif /* MLX5_DRIVER_H */
1177