1 /*
2 * Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #ifndef _MLX4_EN_H_
35 #define _MLX4_EN_H_
36
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/kobject.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_vlan.h>
44 #include <linux/if_ether.h>
45 #ifdef CONFIG_MLX4_EN_DCB
46 #include <linux/dcbnl.h>
47 #endif
48
49 #include <dev/mlx4/device.h>
50 #include <dev/mlx4/qp.h>
51 #include <dev/mlx4/cq.h>
52 #include <dev/mlx4/srq.h>
53 #include <dev/mlx4/doorbell.h>
54 #include <dev/mlx4/cmd.h>
55
56 #include <netinet/tcp_lro.h>
57
58 #include "en_port.h"
59 #include <dev/mlx4/stats.h>
60
61 #define DRV_NAME "mlx4_en"
62
63 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
64
65 /*
66 * Device constants
67 */
68
69
70 #define MLX4_EN_PAGE_SHIFT 12
71 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
72 #define MLX4_NET_IP_ALIGN 2 /* bytes */
73 #define DEF_RX_RINGS 16
74 #define MAX_RX_RINGS 128
75 #define MIN_RX_RINGS 4
76 #define TXBB_SIZE 64
77
78 #ifndef MLX4_EN_MAX_RX_SEGS
79 #define MLX4_EN_MAX_RX_SEGS 1 /* or 8 */
80 #endif
81
82 #ifndef MLX4_EN_MAX_RX_BYTES
83 #define MLX4_EN_MAX_RX_BYTES MCLBYTES
84 #endif
85
86 #define HEADROOM (2048 / TXBB_SIZE + 1)
87 #define INIT_OWNER_BIT 0xffffffff
88 #define STAMP_STRIDE 64
89 #define STAMP_DWORDS (STAMP_STRIDE / 4)
90 #define STAMP_SHIFT 31
91 #define STAMP_VAL 0x7fffffff
92 #define STATS_DELAY (HZ / 4)
93 #define SERVICE_TASK_DELAY (HZ / 4)
94 #define MAX_NUM_OF_FS_RULES 256
95
96 #define MLX4_EN_FILTER_HASH_SHIFT 4
97 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
98
99 #ifdef CONFIG_NET_RX_BUSY_POLL
100 #define LL_EXTENDED_STATS
101 #endif
102
103 /* vlan valid range */
104 #define VLAN_MIN_VALUE 1
105 #define VLAN_MAX_VALUE 4094
106
107 /*
108 * OS related constants and tunables
109 */
110
111 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
112
113 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(PAGE_SIZE)
114 #define MLX4_EN_ALLOC_ORDER get_order(MLX4_EN_ALLOC_SIZE)
115
116 enum mlx4_en_alloc_type {
117 MLX4_EN_ALLOC_NEW = 0,
118 MLX4_EN_ALLOC_REPLACEMENT = 1,
119 };
120
121 /* Maximum ring sizes */
122 #define MLX4_EN_DEF_TX_QUEUE_SIZE 4096
123
124 /* Minimum packet number till arming the CQ */
125 #define MLX4_EN_MIN_RX_ARM 2048
126 #define MLX4_EN_MIN_TX_ARM 2048
127
128 /* Maximum ring sizes */
129 #define MLX4_EN_MAX_TX_SIZE 8192
130 #define MLX4_EN_MAX_RX_SIZE 8192
131
132 /* Minimum ring sizes */
133 #define MLX4_EN_MIN_RX_SIZE (4096 / TXBB_SIZE)
134 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
135
136 #define MLX4_EN_SMALL_PKT_SIZE 64
137
138 #define MLX4_EN_MAX_TX_RING_P_UP 32
139 #define MLX4_EN_NUM_UP 1
140
141 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
142 MLX4_EN_NUM_UP)
143
144 #define MLX4_EN_NO_VLAN 0xffff
145
146 #define MLX4_EN_DEF_TX_RING_SIZE 1024
147 #define MLX4_EN_DEF_RX_RING_SIZE 1024
148
149 /* Target number of bytes to coalesce with interrupt moderation */
150 #define MLX4_EN_RX_COAL_TARGET 44
151 #define MLX4_EN_RX_COAL_TIME 0x10
152
153 #define MLX4_EN_TX_COAL_PKTS 64
154 #define MLX4_EN_TX_COAL_TIME 64
155
156 #define MLX4_EN_RX_RATE_LOW 400000
157 #define MLX4_EN_RX_COAL_TIME_LOW 0
158 #define MLX4_EN_RX_RATE_HIGH 450000
159 #define MLX4_EN_RX_COAL_TIME_HIGH 128
160 #define MLX4_EN_RX_SIZE_THRESH 1024
161 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
162 #define MLX4_EN_SAMPLE_INTERVAL 0
163 #define MLX4_EN_AVG_PKT_SMALL 256
164
165 #define MLX4_EN_AUTO_CONF 0xffff
166
167 #define MLX4_EN_DEF_RX_PAUSE 1
168 #define MLX4_EN_DEF_TX_PAUSE 1
169
170 /* Interval between successive polls in the Tx routine when polling is used
171 instead of interrupts (in per-core Tx rings) - should be power of 2 */
172 #define MLX4_EN_TX_POLL_MODER 16
173 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
174
175 #define MLX4_EN_64_ALIGN (64 - NET_SKB_PAD)
176 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
177 #define HEADER_COPY_SIZE (128)
178 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETHER_HDR_LEN)
179
180 #define MLX4_EN_MIN_MTU 46
181 #define ETH_BCAST 0xffffffffffffULL
182
183 #define MLX4_EN_LOOPBACK_RETRIES 5
184 #define MLX4_EN_LOOPBACK_TIMEOUT 100
185
186 #ifdef MLX4_EN_PERF_STAT
187 /* Number of samples to 'average' */
188 #define AVG_SIZE 128
189 #define AVG_FACTOR 1024
190
191 #define INC_PERF_COUNTER(cnt) (++(cnt))
192 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
193 #define AVG_PERF_COUNTER(cnt, sample) \
194 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
195 #define GET_PERF_COUNTER(cnt) (cnt)
196 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
197
198 #else
199
200 #define INC_PERF_COUNTER(cnt) do {} while (0)
201 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
202 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
203 #define GET_PERF_COUNTER(cnt) (0)
204 #define GET_AVG_PERF_COUNTER(cnt) (0)
205 #endif /* MLX4_EN_PERF_STAT */
206
207 /* Constants for TX flow */
208 enum {
209 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
210 MAX_BF = 256,
211 MIN_PKT_LEN = 17,
212 };
213
214 /*
215 * Configurables
216 */
217
218 enum cq_type {
219 RX = 0,
220 TX = 1,
221 };
222
223
224 /*
225 * Useful macros
226 */
227 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
228 #define XNOR(x, y) (!(x) == !(y))
229 #define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0)
230
231 struct mlx4_en_tx_info {
232 bus_dmamap_t dma_map;
233 struct mbuf *mb;
234 u32 nr_txbb;
235 u32 nr_bytes;
236 };
237
238
239 #define MLX4_EN_BIT_DESC_OWN 0x80000000
240 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
241 #define MLX4_EN_MEMTYPE_PAD 0x100
242 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
243
244
245 struct mlx4_en_tx_desc {
246 struct mlx4_wqe_ctrl_seg ctrl;
247 union {
248 struct mlx4_wqe_data_seg data; /* at least one data segment */
249 struct mlx4_wqe_lso_seg lso;
250 struct mlx4_wqe_inline_seg inl;
251 };
252 };
253
254 #define MLX4_EN_USE_SRQ 0x01000000
255
256 #define MLX4_EN_RX_BUDGET 64
257
258 #define MLX4_EN_TX_MAX_DESC_SIZE 512 /* bytes */
259 #define MLX4_EN_TX_MAX_MBUF_SIZE 65536 /* bytes */
260 #define MLX4_EN_TX_MAX_PAYLOAD_SIZE 65536 /* bytes */
261 #define MLX4_EN_TX_MAX_MBUF_FRAGS \
262 ((MLX4_EN_TX_MAX_DESC_SIZE - 128) / DS_SIZE_ALIGNMENT) /* units */
263 #define MLX4_EN_TX_WQE_MAX_WQEBBS \
264 (MLX4_EN_TX_MAX_DESC_SIZE / TXBB_SIZE) /* units */
265
266 #define MLX4_EN_CX3_LOW_ID 0x1000
267 #define MLX4_EN_CX3_HIGH_ID 0x1005
268
269 struct mlx4_en_tx_ring {
270 spinlock_t tx_lock;
271 bus_dma_tag_t dma_tag;
272 struct mlx4_hwq_resources wqres;
273 u32 size ; /* number of TXBBs */
274 u32 size_mask;
275 u16 stride;
276 u16 cqn; /* index of port CQ associated with this ring */
277 u32 prod;
278 u32 cons;
279 u32 buf_size;
280 u32 doorbell_qpn;
281 u8 *buf;
282 u16 poll_cnt;
283 struct mlx4_en_tx_info *tx_info;
284 u8 queue_index;
285 u32 last_nr_txbb;
286 struct mlx4_qp qp;
287 struct mlx4_qp_context context;
288 int qpn;
289 enum mlx4_qp_state qp_state;
290 struct mlx4_srq dummy;
291 u64 bytes;
292 u64 packets;
293 u64 tx_csum;
294 u64 queue_stopped;
295 u64 oversized_packets;
296 u64 wake_queue;
297 u64 tso_packets;
298 u64 defrag_attempts;
299 struct mlx4_bf bf;
300 bool bf_enabled;
301 int hwtstamp_tx_type;
302 spinlock_t comp_lock;
303 int inline_thold;
304 u64 watchdog_time;
305 };
306
307 struct mlx4_en_rx_desc {
308 struct mlx4_wqe_data_seg data[MLX4_EN_MAX_RX_SEGS];
309 };
310
311 /* the size of the structure above must be power of two */
312 CTASSERT(powerof2(sizeof(struct mlx4_en_rx_desc)));
313
314 struct mlx4_en_rx_mbuf {
315 bus_dmamap_t dma_map;
316 struct mbuf *mbuf;
317 };
318
319 struct mlx4_en_rx_spare {
320 bus_dmamap_t dma_map;
321 struct mbuf *mbuf;
322 bus_dma_segment_t segs[MLX4_EN_MAX_RX_SEGS];
323 };
324
325 struct mlx4_en_rx_ring {
326 struct mlx4_hwq_resources wqres;
327 bus_dma_tag_t dma_tag;
328 struct mlx4_en_rx_spare spare;
329 u32 size ; /* number of Rx descs*/
330 u32 actual_size;
331 u32 size_mask;
332 u16 log_stride;
333 u16 cqn; /* index of port CQ associated with this ring */
334 u32 prod;
335 u32 cons;
336 u32 buf_size;
337 u8 fcs_del;
338 u32 rx_mb_size;
339 u32 rx_mr_key_be;
340 int qpn;
341 u8 *buf;
342 struct mlx4_en_rx_mbuf *mbuf;
343 u64 errors;
344 u64 bytes;
345 u64 packets;
346 #ifdef LL_EXTENDED_STATS
347 u64 yields;
348 u64 misses;
349 u64 cleaned;
350 #endif
351 u64 csum_ok;
352 u64 csum_none;
353 int hwtstamp_rx_filter;
354 int numa_node;
355 struct lro_ctrl lro;
356 };
357
mlx4_en_can_lro(__be16 status)358 static inline int mlx4_en_can_lro(__be16 status)
359 {
360 const __be16 status_all = cpu_to_be16(
361 MLX4_CQE_STATUS_IPV4 |
362 MLX4_CQE_STATUS_IPV4F |
363 MLX4_CQE_STATUS_IPV6 |
364 MLX4_CQE_STATUS_IPV4OPT |
365 MLX4_CQE_STATUS_TCP |
366 MLX4_CQE_STATUS_UDP |
367 MLX4_CQE_STATUS_IPOK);
368 const __be16 status_ipv4_ipok_tcp = cpu_to_be16(
369 MLX4_CQE_STATUS_IPV4 |
370 MLX4_CQE_STATUS_IPOK |
371 MLX4_CQE_STATUS_TCP);
372 const __be16 status_ipv6_ipok_tcp = cpu_to_be16(
373 MLX4_CQE_STATUS_IPV6 |
374 MLX4_CQE_STATUS_IPOK |
375 MLX4_CQE_STATUS_TCP);
376
377 status &= status_all;
378 return (status == status_ipv4_ipok_tcp ||
379 status == status_ipv6_ipok_tcp);
380 }
381
382 struct mlx4_en_cq {
383 struct mlx4_cq mcq;
384 struct mlx4_hwq_resources wqres;
385 int ring;
386 spinlock_t lock;
387 struct net_device *dev;
388 /* Per-core Tx cq processing support */
389 struct timer_list timer;
390 int size;
391 int buf_size;
392 unsigned vector;
393 enum cq_type is_tx;
394 u16 moder_time;
395 u16 moder_cnt;
396 struct mlx4_cqe *buf;
397 struct task cq_task;
398 struct taskqueue *tq;
399 #define MLX4_EN_OPCODE_ERROR 0x1e
400 u32 tot_rx;
401 u32 tot_tx;
402 u32 curr_poll_rx_cpu_id;
403
404 #ifdef CONFIG_NET_RX_BUSY_POLL
405 unsigned int state;
406 #define MLX4_EN_CQ_STATE_IDLE 0
407 #define MLX4_EN_CQ_STATE_NAPI 1 /* NAPI owns this CQ */
408 #define MLX4_EN_CQ_STATE_POLL 2 /* poll owns this CQ */
409 #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL)
410 #define MLX4_EN_CQ_STATE_NAPI_YIELD 4 /* NAPI yielded this CQ */
411 #define MLX4_EN_CQ_STATE_POLL_YIELD 8 /* poll yielded this CQ */
412 #define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD)
413 #define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD)
414 spinlock_t poll_lock; /* protects from LLS/napi conflicts */
415 #endif /* CONFIG_NET_RX_BUSY_POLL */
416 };
417
418 struct mlx4_en_port_profile {
419 u32 flags;
420 u32 tx_ring_num;
421 u32 rx_ring_num;
422 u32 tx_ring_size;
423 u32 rx_ring_size;
424 u8 rx_pause;
425 u8 rx_ppp;
426 u8 tx_pause;
427 u8 tx_ppp;
428 int rss_rings;
429 int inline_thold;
430 };
431
432 struct mlx4_en_profile {
433 int rss_xor;
434 int udp_rss;
435 u8 rss_mask;
436 u32 active_ports;
437 u32 small_pkt_int;
438 u8 no_reset;
439 u8 num_tx_rings_p_up;
440 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
441 };
442
443 struct mlx4_en_dev {
444 struct mlx4_dev *dev;
445 struct pci_dev *pdev;
446 struct mutex state_lock;
447 struct net_device *pndev[MLX4_MAX_PORTS + 1];
448 u32 port_cnt;
449 bool device_up;
450 struct mlx4_en_profile profile;
451 u32 LSO_support;
452 struct workqueue_struct *workqueue;
453 struct device *dma_device;
454 void __iomem *uar_map;
455 struct mlx4_uar priv_uar;
456 struct mlx4_mr mr;
457 u32 priv_pdn;
458 spinlock_t uar_lock;
459 u8 mac_removed[MLX4_MAX_PORTS + 1];
460 unsigned long last_overflow_check;
461 unsigned long overflow_period;
462 };
463
464
465 struct mlx4_en_rss_map {
466 int base_qpn;
467 struct mlx4_qp qps[MAX_RX_RINGS];
468 enum mlx4_qp_state state[MAX_RX_RINGS];
469 struct mlx4_qp indir_qp;
470 enum mlx4_qp_state indir_state;
471 };
472
473 enum mlx4_en_port_flag {
474 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
475 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
476 };
477
478 struct mlx4_en_port_state {
479 int link_state;
480 int link_speed;
481 int transceiver;
482 u32 flags;
483 };
484
485 enum mlx4_en_addr_list_act {
486 MLX4_ADDR_LIST_NONE,
487 MLX4_ADDR_LIST_REM,
488 MLX4_ADDR_LIST_ADD,
489 };
490
491 struct mlx4_en_addr_list {
492 struct list_head list;
493 enum mlx4_en_addr_list_act action;
494 u8 addr[ETH_ALEN];
495 u64 reg_id;
496 u64 tunnel_reg_id;
497 };
498
499 #ifdef CONFIG_MLX4_EN_DCB
500 /* Minimal TC BW - setting to 0 will block traffic */
501 #define MLX4_EN_BW_MIN 1
502 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
503
504 #define MLX4_EN_TC_VENDOR 0
505 #define MLX4_EN_TC_ETS 7
506
507 #endif
508
509
510 enum {
511 MLX4_EN_FLAG_PROMISC = (1 << 0),
512 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
513 /* whether we need to enable hardware loopback by putting dmac
514 * in Tx WQE
515 */
516 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
517 /* whether we need to drop packets that hardware loopback-ed */
518 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
519 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4),
520 #ifdef CONFIG_MLX4_EN_DCB
521 MLX4_EN_FLAG_DCB_ENABLED = (1 << 5)
522 #endif
523 };
524
525 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
526 #define MLX4_EN_MAC_HASH_IDX 5
527
528 struct en_port {
529 struct kobject kobj;
530 struct mlx4_dev *dev;
531 u8 port_num;
532 u8 vport_num;
533 };
534
535 struct mlx4_en_priv {
536 struct mlx4_en_dev *mdev;
537 struct mlx4_en_port_profile *prof;
538 struct net_device *dev;
539 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
540 struct mlx4_en_port_state port_state;
541 spinlock_t stats_lock;
542 /* To allow rules removal while port is going down */
543 struct list_head ethtool_list;
544
545 unsigned long last_moder_packets[MAX_RX_RINGS];
546 unsigned long last_moder_tx_packets;
547 unsigned long last_moder_bytes[MAX_RX_RINGS];
548 unsigned long last_moder_jiffies;
549 int last_moder_time[MAX_RX_RINGS];
550 u16 rx_usecs;
551 u16 rx_frames;
552 u16 tx_usecs;
553 u16 tx_frames;
554 u32 pkt_rate_low;
555 u32 rx_usecs_low;
556 u32 pkt_rate_high;
557 u32 rx_usecs_high;
558 u32 sample_interval;
559 u32 adaptive_rx_coal;
560 u32 msg_enable;
561 u32 loopback_ok;
562 u32 validate_loopback;
563
564 struct mlx4_hwq_resources res;
565 int link_state;
566 int last_link_state;
567 bool port_up;
568 int port;
569 int registered;
570 int gone;
571 int allocated;
572 unsigned char current_mac[ETH_ALEN + 2];
573 u64 mac;
574 int mac_index;
575 unsigned max_mtu;
576 int base_qpn;
577 int cqe_factor;
578
579 struct mlx4_en_rss_map rss_map;
580 u32 flags;
581 u8 num_tx_rings_p_up;
582 u32 tx_ring_num;
583 u32 rx_ring_num;
584 u32 rx_mb_size;
585
586 struct mlx4_en_tx_ring **tx_ring;
587 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
588 struct mlx4_en_cq **tx_cq;
589 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
590 struct mlx4_qp drop_qp;
591 struct work_struct rx_mode_task;
592 struct work_struct watchdog_task;
593 struct work_struct linkstate_task;
594 struct delayed_work stats_task;
595 struct delayed_work service_task;
596 struct mlx4_en_perf_stats pstats;
597 struct mlx4_en_pkt_stats pkstats;
598 struct mlx4_en_pkt_stats pkstats_last;
599 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
600 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
601 struct mlx4_en_flow_stats_rx rx_flowstats;
602 struct mlx4_en_flow_stats_tx tx_flowstats;
603 struct mlx4_en_port_stats port_stats;
604 struct mlx4_en_vport_stats vport_stats;
605 struct mlx4_en_vf_stats vf_stats;
606 struct list_head mc_list;
607 struct list_head uc_list;
608 struct list_head curr_mc_list;
609 struct list_head curr_uc_list;
610 u64 broadcast_id;
611 struct mlx4_en_stat_out_mbox hw_stats;
612 int vids[128];
613 bool wol;
614 struct device *ddev;
615 struct dentry *dev_root;
616 u32 counter_index;
617 eventhandler_tag vlan_attach;
618 eventhandler_tag vlan_detach;
619 struct callout watchdog_timer;
620 struct ifmedia media;
621 volatile int blocked;
622 struct sysctl_oid *conf_sysctl;
623 struct sysctl_oid *stat_sysctl;
624 struct sysctl_ctx_list conf_ctx;
625 struct sysctl_ctx_list stat_ctx;
626
627 #ifdef CONFIG_MLX4_EN_DCB
628 struct ieee_ets ets;
629 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
630 u8 dcbx_cap;
631 #endif
632 #ifdef CONFIG_RFS_ACCEL
633 spinlock_t filters_lock;
634 int last_filter_id;
635 struct list_head filters;
636 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
637 #endif
638 u64 tunnel_reg_id;
639 struct en_port *vf_ports[MLX4_MAX_NUM_VF];
640 unsigned long last_ifq_jiffies;
641 u64 if_counters_rx_errors;
642 u64 if_counters_rx_no_buffer;
643 };
644
645 enum mlx4_en_wol {
646 MLX4_EN_WOL_MAGIC = (1ULL << 61),
647 MLX4_EN_WOL_ENABLED = (1ULL << 62),
648 };
649
650 struct mlx4_mac_entry {
651 struct hlist_node hlist;
652 unsigned char mac[ETH_ALEN + 2];
653 u64 reg_id;
654 };
655
mlx4_en_get_cqe(u8 * buf,int idx,int cqe_sz)656 static inline struct mlx4_cqe *mlx4_en_get_cqe(u8 *buf, int idx, int cqe_sz)
657 {
658 return (struct mlx4_cqe *)(buf + idx * cqe_sz);
659 }
660
661 #ifdef CONFIG_NET_RX_BUSY_POLL
mlx4_en_cq_init_lock(struct mlx4_en_cq * cq)662 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
663 {
664 spin_lock_init(&cq->poll_lock);
665 cq->state = MLX4_EN_CQ_STATE_IDLE;
666 }
667
668 /* called from the device poll rutine to get ownership of a cq */
mlx4_en_cq_lock_napi(struct mlx4_en_cq * cq)669 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
670 {
671 int rc = true;
672 spin_lock(&cq->poll_lock);
673 if (cq->state & MLX4_CQ_LOCKED) {
674 WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI);
675 cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD;
676 rc = false;
677 } else
678 /* we don't care if someone yielded */
679 cq->state = MLX4_EN_CQ_STATE_NAPI;
680 spin_unlock(&cq->poll_lock);
681 return rc;
682 }
683
684 /* returns true is someone tried to get the cq while napi had it */
mlx4_en_cq_unlock_napi(struct mlx4_en_cq * cq)685 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
686 {
687 int rc = false;
688 spin_lock(&cq->poll_lock);
689 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL |
690 MLX4_EN_CQ_STATE_NAPI_YIELD));
691
692 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
693 rc = true;
694 cq->state = MLX4_EN_CQ_STATE_IDLE;
695 spin_unlock(&cq->poll_lock);
696 return rc;
697 }
698
699 /* called from mlx4_en_low_latency_poll() */
mlx4_en_cq_lock_poll(struct mlx4_en_cq * cq)700 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
701 {
702 int rc = true;
703 spin_lock_bh(&cq->poll_lock);
704 if ((cq->state & MLX4_CQ_LOCKED)) {
705 struct net_device *dev = cq->dev;
706 struct mlx4_en_priv *priv = netdev_priv(dev);
707 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
708
709 cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD;
710 rc = false;
711 #ifdef LL_EXTENDED_STATS
712 rx_ring->yields++;
713 #endif
714 } else
715 /* preserve yield marks */
716 cq->state |= MLX4_EN_CQ_STATE_POLL;
717 spin_unlock_bh(&cq->poll_lock);
718 return rc;
719 }
720
721 /* returns true if someone tried to get the cq while it was locked */
mlx4_en_cq_unlock_poll(struct mlx4_en_cq * cq)722 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
723 {
724 int rc = false;
725 spin_lock_bh(&cq->poll_lock);
726 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI));
727
728 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
729 rc = true;
730 cq->state = MLX4_EN_CQ_STATE_IDLE;
731 spin_unlock_bh(&cq->poll_lock);
732 return rc;
733 }
734
735 /* true if a socket is polling, even if it did not get the lock */
mlx4_en_cq_busy_polling(struct mlx4_en_cq * cq)736 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
737 {
738 WARN_ON(!(cq->state & MLX4_CQ_LOCKED));
739 return cq->state & CQ_USER_PEND;
740 }
741 #else
mlx4_en_cq_init_lock(struct mlx4_en_cq * cq)742 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
743 {
744 }
745
mlx4_en_cq_lock_napi(struct mlx4_en_cq * cq)746 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
747 {
748 return true;
749 }
750
mlx4_en_cq_unlock_napi(struct mlx4_en_cq * cq)751 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
752 {
753 return false;
754 }
755
mlx4_en_cq_lock_poll(struct mlx4_en_cq * cq)756 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
757 {
758 return false;
759 }
760
mlx4_en_cq_unlock_poll(struct mlx4_en_cq * cq)761 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
762 {
763 return false;
764 }
765
mlx4_en_cq_busy_polling(struct mlx4_en_cq * cq)766 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
767 {
768 return false;
769 }
770 #endif /* CONFIG_NET_RX_BUSY_POLL */
771
772 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
773
774 void mlx4_en_destroy_netdev(struct net_device *dev);
775 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
776 struct mlx4_en_port_profile *prof);
777
778 int mlx4_en_start_port(struct net_device *dev);
779 void mlx4_en_stop_port(struct net_device *dev);
780
781 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
782 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
783
784 int mlx4_en_pre_config(struct mlx4_en_priv *priv);
785 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
786 int entries, int ring, enum cq_type mode, int node);
787 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
788 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
789 int cq_idx);
790 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
791 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
792 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
793
794 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
795 u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb);
796
797 int mlx4_en_transmit(struct ifnet *dev, struct mbuf *m);
798 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
799 struct mlx4_en_tx_ring **pring,
800 u32 size, u16 stride, int node, int queue_idx);
801 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
802 struct mlx4_en_tx_ring **pring);
803 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
804 struct mlx4_en_tx_ring *ring,
805 int cq, int user_prio);
806 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
807 struct mlx4_en_tx_ring *ring);
808 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
809 void mlx4_en_qflush(struct ifnet *dev);
810
811 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
812 struct mlx4_en_rx_ring **pring,
813 u32 size, int node);
814 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
815 struct mlx4_en_rx_ring **pring,
816 u32 size);
817 void mlx4_en_rx_que(void *context, int pending);
818 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
819 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
820 struct mlx4_en_rx_ring *ring);
821 int mlx4_en_process_rx_cq(struct net_device *dev,
822 struct mlx4_en_cq *cq,
823 int budget);
824 void mlx4_en_poll_tx_cq(unsigned long data);
825 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
826 int is_tx, int rss, int qpn, int cqn, int user_prio,
827 struct mlx4_qp_context *context);
828 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
829 int mlx4_en_map_buffer(struct mlx4_buf *buf);
830 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
831 void mlx4_en_calc_rx_buf(struct net_device *dev);
832
833 const u32 *mlx4_en_get_rss_key(struct mlx4_en_priv *priv, u16 *keylen);
834 u8 mlx4_en_get_rss_mask(struct mlx4_en_priv *priv);
835 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
836 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
837 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
838 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
839 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
840 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
841
842 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
843
844 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
845 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
846 int mlx4_en_get_vport_stats(struct mlx4_en_dev *mdev, u8 port);
847 void mlx4_en_create_debug_files(struct mlx4_en_priv *priv);
848 void mlx4_en_delete_debug_files(struct mlx4_en_priv *priv);
849 int mlx4_en_register_debugfs(void);
850 void mlx4_en_unregister_debugfs(void);
851
852 #ifdef CONFIG_MLX4_EN_DCB
853 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
854 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
855 #endif
856
857 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
858
859 #ifdef CONFIG_RFS_ACCEL
860 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv,
861 struct mlx4_en_rx_ring *rx_ring);
862 #endif
863
864 #define MLX4_EN_NUM_SELF_TEST 5
865 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
866 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
867
868 /*
869 * Functions for time stamping
870 */
871 #define SKBTX_HW_TSTAMP (1 << 0)
872 #define SKBTX_IN_PROGRESS (1 << 2)
873
874 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
875
876 /* Functions for caching and restoring statistics */
877 int mlx4_en_get_sset_count(struct net_device *dev, int sset);
878 void mlx4_en_restore_ethtool_stats(struct mlx4_en_priv *priv,
879 u64 *data);
880
881 /*
882 * Globals
883 */
884 extern const struct ethtool_ops mlx4_en_ethtool_ops;
885
886 /*
887 * Defines for link speed - needed by selftest
888 */
889 #define MLX4_EN_LINK_SPEED_1G 1000
890 #define MLX4_EN_LINK_SPEED_10G 10000
891 #define MLX4_EN_LINK_SPEED_40G 40000
892
893 enum {
894 NETIF_MSG_DRV = 0x0001,
895 NETIF_MSG_PROBE = 0x0002,
896 NETIF_MSG_LINK = 0x0004,
897 NETIF_MSG_TIMER = 0x0008,
898 NETIF_MSG_IFDOWN = 0x0010,
899 NETIF_MSG_IFUP = 0x0020,
900 NETIF_MSG_RX_ERR = 0x0040,
901 NETIF_MSG_TX_ERR = 0x0080,
902 NETIF_MSG_TX_QUEUED = 0x0100,
903 NETIF_MSG_INTR = 0x0200,
904 NETIF_MSG_TX_DONE = 0x0400,
905 NETIF_MSG_RX_STATUS = 0x0800,
906 NETIF_MSG_PKTDATA = 0x1000,
907 NETIF_MSG_HW = 0x2000,
908 NETIF_MSG_WOL = 0x4000,
909 };
910
911
912 /*
913 * printk / logging functions
914 */
915
916 #define en_print(level, priv, format, arg...) \
917 { \
918 if ((priv)->registered) \
919 printk(level "%s: %s: " format, DRV_NAME, \
920 (priv)->dev->if_xname, ## arg); \
921 else \
922 printk(level "%s: %s: Port %d: " format, \
923 DRV_NAME, dev_name(&(priv)->mdev->pdev->dev), \
924 (priv)->port, ## arg); \
925 }
926
927
928 #define en_dbg(mlevel, priv, format, arg...) \
929 do { \
930 if (NETIF_MSG_##mlevel & priv->msg_enable) \
931 en_print(KERN_DEBUG, priv, format, ##arg); \
932 } while (0)
933 #define en_warn(priv, format, arg...) \
934 en_print(KERN_WARNING, priv, format, ##arg)
935 #define en_err(priv, format, arg...) \
936 en_print(KERN_ERR, priv, format, ##arg)
937 #define en_info(priv, format, arg...) \
938 en_print(KERN_INFO, priv, format, ## arg)
939
940 #define mlx4_err(mdev, format, arg...) \
941 pr_err("%s %s: " format, DRV_NAME, \
942 dev_name(&(mdev)->pdev->dev), ##arg)
943 #define mlx4_info(mdev, format, arg...) \
944 pr_info("%s %s: " format, DRV_NAME, \
945 dev_name(&(mdev)->pdev->dev), ##arg)
946 #define mlx4_warn(mdev, format, arg...) \
947 pr_warning("%s %s: " format, DRV_NAME, \
948 dev_name(&(mdev)->pdev->dev), ##arg)
949
950 #endif
951