Searched refs:MIPS32 (Results 1 – 25 of 38) sorted by relevance
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52 to MIPS32 to compute addresses for the static relocation model.80 for the difference in the results of instruction execution. On MIPS32,
105 "Subset of MIPS-III that is also in MIPS32 "116 "Subset of MIPS-IV that is also in MIPS32 "
52 On MIPS32, the copy_u.d intrinsic will emit this instruction instead of
306 // MIPS32 arithmetic instructions sign extend their result implicitly.
386 // The portions of MIPS-III that were also added to MIPS32392 // The portions of MIPS-III that were also added to MIPS32 but were removed in399 // The portions of MIPS-III that were also added to MIPS32405 // The portions of MIPS-IV that were also added to MIPS32.411 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
907 // MIPS32 arithmetic instructions sign extend their result implicitly.
603 // MIPS32 EVA
1 ;; DFA-based pipeline descriptions for MIPS32 4K processor family6 ;; "MIPS32 4K Processor Core Family Software User's Manual,
1 ;; DFA-based pipeline descriptions for MIPS32 5K processor family
9 ;; "MIPS32 24K Processor Core Family Software User's Manual, Rev 3.04."
24 >0 lelong&0xf0000000 0x50000000 MIPS3226 >0 lelong&0xf0000000 0x70000000 MIPS32 rel228 >0 lelong&0xf0000000 0x90000000 MIPS32 rel6
34 # Intrng compatible MIPS32 interrupt controller
18 different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,92 @sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64},132 Enables the SmartMIPS extensions to the MIPS32 instruction set, which533 MIPS32 @sc{isa} from that point on in the assembly. The
1325 for MIPS32 support, and clean up existing entries for1326 aesthetics, consistency with the MIPS32 ISA, and1341 Enable "ssnop" for MIPS32. Add "break" variant with 20 bit1342 code for MIPS32. Update "clo" and "clz" to use 'U' operand1344 "mfc2," "mfc3," "mtc1," "mtc2," and "mtc3" for MIPS32. Update1345 MIPS32 "sdbbp" to use 'B' operand specifier. Add MIPS321352 MIPS32.1457 Add msub and msubu instructions for MIPS32.1458 Add madd/maddu aliases for mad/madu for MIPS32.1459 Support wait, deret, eret, movn, pref for MIPS32.
474 decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
846 forms of "sll". Add new MIPS32 Release 2 instructions: ehb,850 used on MIPS32 Release 2, and add the official mnemonics
89 MIPS32 = 0x12, enumerator
147 CV_ENUM_CLASS_ENT(CPUType, MIPS32),
170 * Support for the MIPS32, by Anders Norlander.
1122 * readelf.c (get_machine_flags): Recognize MIPS32 ISA in1234 * NEWS: Mention support for MIPS32.
226 RETURN_CASE(CPUType, MIPS32, "mips-32"); in formatMachineType()
117 * Added support for MIPS32 Release 2.
2277 * NEWS: Belatedly mention support for MIPS32 Release 2.3009 and "+C" operands for MIPS32 Release 2 ins/ext instructions.3010 Implement "K" operand for MIPS32 Release 2 rdhwr instruction.3020 (mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
788 (INSN_MIPS32): New define for MIPS32 extensions.789 (OPCODE_IS_MEMBER): Recognize MIPS32 instructions.
411 # refer to contemporary MIPS Architecture specifications, MIPS32 and678 …_VSB_CONFIG_FILE=\"\$(WIND_BASE)/target/lib/h/config/vsbConfig.h\" -DCPU=MIPS32 -msoft-float -mno-…