Searched refs:MC_SEQ_MISC0_GDDR5_MASK (Results 1 – 2 of 2) sorted by relevance
172 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 macro
249 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT; in ni_mc_load_microcode()