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Searched refs:Lat (Results 1 – 22 of 22) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMScheduleA57WriteRes.td58 foreach Lat = 3-20 in {
59 def A57Write_#Lat#cyc_1L : SchedWriteRes<[A57UnitL]> {
60 let Latency = Lat;
65 foreach Lat = 4-16 in {
66 def A57Write_#Lat#cyc_1S : SchedWriteRes<[A57UnitS]> {
67 let Latency = Lat;
238 foreach Lat = 3-20 in {
239 def A57Write_#Lat#cyc_1L_1I : SchedWriteRes<[A57UnitL, A57UnitI]> {
240 let Latency = Lat; let NumMicroOps = 2;
265 foreach Lat = 4-16 in {
[all …]
HDARMScheduleR52.td346 foreach Lat = 3-25 in {
347 def R52WriteILDM#Lat#Cy : SchedWriteRes<[R52UnitLd]> {
348 let Latency = Lat;
350 def R52WriteILDM#Lat#CyNo : SchedWriteRes<[]> {
351 let Latency = Lat;
546 foreach Lat = 1-32 in {
547 def R52WriteLM#Lat#Cy : SchedWriteRes<[]> {
548 let Latency = Lat;
HDARMScheduleSwift.td382 foreach Lat = 3-25 in {
383 def SwiftWriteLM#Lat#Cy : SchedWriteRes<[SwiftUnitP2]> {
384 let Latency = Lat;
386 def SwiftWriteLM#Lat#CyNo : SchedWriteRes<[]> {
387 let Latency = Lat;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDAMDGPUSubtarget.cpp733 unsigned Lat = 0; in adjustSchedDependency() local
736 Lat = InstrInfo.getInstrLatency(getInstrItineraryData(), *I); in adjustSchedDependency()
737 else if (Lat) in adjustSchedDependency()
738 --Lat; in adjustSchedDependency()
740 Dep.setLatency(Lat); in adjustSchedDependency()
746 unsigned Lat = InstrInfo.getInstrLatency(getInstrItineraryData(), *SrcI); in adjustSchedDependency() local
747 for (++I; I != E && I->isBundledWithPred() && Lat; ++I) { in adjustSchedDependency()
750 --Lat; in adjustSchedDependency()
752 Dep.setLatency(Lat); in adjustSchedDependency()
906 unsigned Lat = TSchedModel->computeInstrLatency(&MAI) - 1; in apply() local
[all …]
HDSIInstrInfo.cpp6637 unsigned Lat = 0, Count = 0; in getInstrLatency() local
6640 Lat = std::max(Lat, SchedModel.computeInstrLatency(&*I)); in getInstrLatency()
6642 return Lat + Count - 1; in getInstrLatency()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86ScheduleBdVer2.td191 list<ProcResourceKind> ExePorts, int Lat = 1,
194 let Latency = Lat;
201 list<ProcResourceKind> ExePorts, int Lat,
204 defm : PdWriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
208 !add(Lat, LoadLat),
219 list<ProcResourceKind> ExePorts, int Lat = 1,
222 defm : __pdWriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
227 list<ProcResourceKind> ExePorts, int Lat = 1,
230 defm : __pdWriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
235 list<ProcResourceKind> ExePorts, int Lat,
[all …]
HDX86ScheduleBtVer2.td123 int Lat, list<int> Res = [], int UOps = 1,
127 let Latency = Lat;
135 let Latency = !add(Lat, 3);
143 int Lat, list<int> Res = [], int UOps = 1,
147 let Latency = Lat;
155 let Latency = !add(Lat, 5);
163 int Lat, list<int> Res = [2], int UOps = 2,
167 let Latency = Lat;
175 let Latency = !add(Lat, 5);
HDX86ScheduleSLM.td64 int Lat, list<int> Res = [1], int UOps = 1,
68 let Latency = Lat;
76 let Latency = !add(Lat, LoadLat);
HDX86ScheduleZnver2.td133 int Lat, list<int> Res = [], int UOps = 1,
137 let Latency = Lat;
145 let Latency = !add(Lat, LoadLat);
154 int Lat, list<int> Res = [], int UOps = 1,
158 let Latency = Lat;
166 let Latency = !add(Lat, LoadLat);
HDX86ScheduleZnver1.td134 int Lat, list<int> Res = [], int UOps = 1,
138 let Latency = Lat;
146 let Latency = !add(Lat, LoadLat);
155 int Lat, list<int> Res = [], int UOps = 1,
159 let Latency = Lat;
167 let Latency = !add(Lat, LoadLat);
HDX86SchedSandyBridge.td88 int Lat, list<int> Res = [1], int UOps = 1,
92 let Latency = Lat;
100 let Latency = !add(Lat, LoadLat);
HDX86Schedule.td33 int Lat, list<int> Res, int UOps> {
35 let Latency = Lat;
HDX86SchedBroadwell.td93 int Lat, list<int> Res = [1], int UOps = 1,
97 let Latency = Lat;
105 let Latency = !add(Lat, LoadLat);
HDX86SchedSkylakeClient.td92 int Lat, list<int> Res = [1], int UOps = 1,
96 let Latency = Lat;
104 let Latency = !add(Lat, LoadLat);
HDX86SchedHaswell.td98 int Lat, list<int> Res = [1], int UOps = 1,
102 let Latency = Lat;
110 let Latency = !add(Lat, LoadLat);
HDX86SchedSkylakeServer.td92 int Lat, list<int> Res = [1], int UOps = 1,
96 let Latency = Lat;
104 let Latency = !add(Lat, LoadLat);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonSubtarget.cpp457 void HexagonSubtarget::changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) in changeLatency()
463 I.setLatency(Lat); in changeLatency()
469 F->setLatency(Lat); in changeLatency()
HDHexagonSubtarget.h273 void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDScheduleDAG.h147 void setLatency(unsigned Lat) { in setLatency() argument
148 Latency = Lat; in setLatency()
/freebsd-11-stable/contrib/ntp/ntpd/
HDrefclock_oncore.c3119 double Lat, Lon, Ht; in oncore_get_timestamp() local
3126 Lat = lat; in oncore_get_timestamp()
3130 Lat /= 3600000; in oncore_get_timestamp()
3135 "Ga Posn Lat = %.7f, Lon = %.7f, Ht = %.2f", Lat, in oncore_get_timestamp()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDMachinePipeliner.cpp1132 unsigned Lat = D.getLatency(); in swapAntiDependences() local
1135 Dep.setLatency(Lat); in swapAntiDependences()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
HDP9InstrResources.td1310 (instregex "gBC(A|Aat|CTR|CTRL|L|LA|LAat|LR|LRL|Lat|at)?$"),