| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| HD | CombinerHelper.h | 122 bool matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef,
126 void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef,
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| HD | CombinerHelper.cpp | 116 bool IsUndef = false; in tryCombineConcatVectors() local
118 if (matchCombineConcatVectors(MI, IsUndef, Ops)) { in tryCombineConcatVectors()
119 applyCombineConcatVectors(MI, IsUndef, Ops); in tryCombineConcatVectors()
125 bool CombinerHelper::matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef, in matchCombineConcatVectors() argument
129 IsUndef = true; in matchCombineConcatVectors()
141 IsUndef = false; in matchCombineConcatVectors()
171 MachineInstr &MI, bool IsUndef, const ArrayRef<Register> Ops) { in applyCombineConcatVectors() argument
184 if (IsUndef) in applyCombineConcatVectors()
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| HD | MachineOperand.h | 130 unsigned IsUndef : 1; variable
395 return IsUndef; in isUndef()
511 IsUndef = Val;
793 Op.IsUndef = isUndef;
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| HD | MachineInstr.h | 1422 void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| HD | SIShrinkInstructions.cpp | 250 bool IsUndef = true; in shrinkMIMG() local
262 IsUndef = false; in shrinkMIMG()
297 MI.getOperand(VAddr0Idx).setIsUndef(IsUndef); in shrinkMIMG()
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| HD | GCNHazardRecognizer.cpp | 895 bool IsUndef = Src0->isUndef(); in fixVcmpxPermlaneHazards() local
898 .addReg(Reg, RegState::Define | (IsUndef ? RegState::Dead : 0)) in fixVcmpxPermlaneHazards()
899 .addReg(Reg, IsUndef ? RegState::Undef : RegState::Kill); in fixVcmpxPermlaneHazards()
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| HD | SIInstrInfo.cpp | 1492 bool IsUndef = MI.getOperand(1).isUndef(); in expandPostRAPseudo() local
1502 RegState::Implicit | (IsUndef ? RegState::Undef : 0)); in expandPostRAPseudo()
1658 bool IsUndef = RegOp.isUndef(); in swapRegAndNonRegOperand() local
1668 NonRegOp.ChangeToRegister(Reg, false, false, IsKill, IsDead, IsUndef, IsDebug); in swapRegAndNonRegOperand()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| HD | HexagonISelLoweringHVX.cpp | 376 bool IsSplat = true, IsUndef = true; in buildHvxVectorReg() local
381 IsUndef = false; in buildHvxVectorReg()
387 if (IsUndef) in buildHvxVectorReg()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| HD | MachineInstr.cpp | 1925 void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) { in setRegisterDefReadUndef() argument
1929 MO.setIsUndef(IsUndef); in setRegisterDefReadUndef()
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| HD | RegisterCoalescer.cpp | 1659 bool IsUndef = true; in addUndefFlag() local
1664 IsUndef = false; in addUndefFlag()
1668 if (IsUndef) { in addUndefFlag()
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| HD | MachineOperand.cpp | 256 IsUndef = isUndef; in ChangeToRegister()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| HD | AArch64InstrInfo.cpp | 2970 bool IsUndef = true; in loadRegPairFromStackSlot() local
2976 IsUndef = false; in loadRegPairFromStackSlot()
2979 .addReg(DestReg0, RegState::Define | getUndefRegState(IsUndef), SubIdx0) in loadRegPairFromStackSlot()
2980 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1) in loadRegPairFromStackSlot()
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| /freebsd-11-stable/contrib/llvm-project/clang/lib/Serialization/ |
| HD | ASTReader.cpp | 589 bool IsUndef = PPOpts.Macros[I].second; in collectMacroDefinitions() local
596 if (IsUndef) { in collectMacroDefinitions()
5825 bool IsUndef = Record[Idx++]; in ParsePreprocessorOptions() local
5826 PPOpts.Macros.push_back(std::make_pair(Macro, IsUndef)); in ParsePreprocessorOptions()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| HD | X86ISelLowering.cpp | 5538 bool IsUndef = Values[i] < 0 && IsMask; in getConstVector() local
5539 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) : in getConstVector()
5543 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) : in getConstVector()
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