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Searched refs:InsElt (Results 1 – 5 of 5) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
HDInstCombineVectorOps.cpp522 static void replaceExtractElements(InsertElementInst *InsElt, in replaceExtractElements() argument
525 VectorType *InsVecType = InsElt->getType(); in replaceExtractElements()
540 IntegerType *IntType = Type::getInt32Ty(InsElt->getContext()); in replaceExtractElements()
561 if (InsertionBlock != InsElt->getParent()) in replaceExtractElements()
569 if (InsElt->hasOneUse() && isa<InsertElementInst>(InsElt->user_back())) in replaceExtractElements()
747 static Instruction *foldInsSequenceIntoSplat(InsertElementInst &InsElt) { in foldInsSequenceIntoSplat() argument
750 if (InsElt.hasOneUse() && isa<InsertElementInst>(InsElt.user_back())) in foldInsSequenceIntoSplat()
753 auto *VecTy = cast<VectorType>(InsElt.getType()); in foldInsSequenceIntoSplat()
761 Value *SplatVal = InsElt.getOperand(1); in foldInsSequenceIntoSplat()
762 InsertElementInst *CurrIE = &InsElt; in foldInsSequenceIntoSplat()
[all …]
HDInstCombineCasts.cpp664 auto *InsElt = dyn_cast<InsertElementInst>(Trunc.getOperand(0)); in shrinkInsertElt() local
665 if (!InsElt || !InsElt->hasOneUse()) in shrinkInsertElt()
670 Value *VecOp = InsElt->getOperand(0); in shrinkInsertElt()
671 Value *ScalarOp = InsElt->getOperand(1); in shrinkInsertElt()
672 Value *Index = InsElt->getOperand(2); in shrinkInsertElt()
2501 if (auto *InsElt = dyn_cast<InsertElementInst>(Src)) in visitBitCast() local
2502 return new BitCastInst(InsElt->getOperand(1), DestTy); in visitBitCast()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64InstructionSelector.cpp3417 auto InsElt = in emitVectorConcat() local
3423 constrainSelectedInstRegOperands(*InsElt, TII, TRI, RBI); in emitVectorConcat()
3424 return &*InsElt; in emitVectorConcat()
3868 MachineInstr *InsElt = nullptr; in emitLaneInsert() local
3881 InsElt = MIRBuilder.buildInstr(Opc, {*DstReg}, {SrcReg}) in emitLaneInsert()
3886 InsElt = MIRBuilder.buildInstr(Opc, {*DstReg}, {SrcReg}) in emitLaneInsert()
3891 constrainSelectedInstRegOperands(*InsElt, TII, TRI, RBI); in emitLaneInsert()
3892 return InsElt; in emitLaneInsert()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMISelLowering.cpp13011 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT, in PerformInsertEltCombine() local
13013 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt); in PerformInsertEltCombine()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
HDDAGCombiner.cpp19197 if (SDValue InsElt = replaceShuffleOfInsert(SVN, DAG)) in visitVECTOR_SHUFFLE() local
19198 return InsElt; in visitVECTOR_SHUFFLE()