1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD$ 31 */ 32 33 #ifndef _MACHINE_SPECIALREG_H_ 34 #define _MACHINE_SPECIALREG_H_ 35 36 /* 37 * Bits in 386 special registers: 38 */ 39 #define CR0_PE 0x00000001 /* Protected mode Enable */ 40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43 #define CR0_PG 0x80000000 /* PaGing enable */ 44 45 /* 46 * Bits in 486 special registers: 47 */ 48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50 all modes) */ 51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52 #define CR0_NW 0x20000000 /* Not Write-through */ 53 #define CR0_CD 0x40000000 /* Cache Disable */ 54 55 #define CR3_PCID_SAVE 0x8000000000000000 56 #define CR3_PCID_MASK 0xfff 57 58 /* 59 * Bits in PPro special registers 60 */ 61 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 62 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 63 #define CR4_TSD 0x00000004 /* Time stamp disable */ 64 #define CR4_DE 0x00000008 /* Debugging extensions */ 65 #define CR4_PSE 0x00000010 /* Page size extensions */ 66 #define CR4_PAE 0x00000020 /* Physical address extension */ 67 #define CR4_MCE 0x00000040 /* Machine check enable */ 68 #define CR4_PGE 0x00000080 /* Page global enable */ 69 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 70 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 71 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 72 #define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */ 73 #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */ 74 #define CR4_PCIDE 0x00020000 /* Enable Context ID */ 75 #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ 76 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */ 77 #define CR4_SMAP 0x00200000 /* Supervisor-Mode Access Prevention */ 78 79 /* 80 * Bits in AMD64 special registers. EFER is 64 bits wide. 81 */ 82 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 83 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 84 #define EFER_LMA 0x000000400 /* Long mode active (R) */ 85 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 86 #define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */ 87 #define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */ 88 #define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */ 89 #define EFER_TCE 0x000008000 /* Translation Cache Extension */ 90 91 /* 92 * Intel Extended Features registers 93 */ 94 #define XCR0 0 /* XFEATURE_ENABLED_MASK register */ 95 96 #define XFEATURE_ENABLED_X87 0x00000001 97 #define XFEATURE_ENABLED_SSE 0x00000002 98 #define XFEATURE_ENABLED_YMM_HI128 0x00000004 99 #define XFEATURE_ENABLED_AVX XFEATURE_ENABLED_YMM_HI128 100 #define XFEATURE_ENABLED_BNDREGS 0x00000008 101 #define XFEATURE_ENABLED_BNDCSR 0x00000010 102 #define XFEATURE_ENABLED_OPMASK 0x00000020 103 #define XFEATURE_ENABLED_ZMM_HI256 0x00000040 104 #define XFEATURE_ENABLED_HI16_ZMM 0x00000080 105 106 #define XFEATURE_AVX \ 107 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX) 108 #define XFEATURE_AVX512 \ 109 (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 | \ 110 XFEATURE_ENABLED_HI16_ZMM) 111 #define XFEATURE_MPX \ 112 (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR) 113 114 /* 115 * CPUID instruction features register 116 */ 117 #define CPUID_FPU 0x00000001 118 #define CPUID_VME 0x00000002 119 #define CPUID_DE 0x00000004 120 #define CPUID_PSE 0x00000008 121 #define CPUID_TSC 0x00000010 122 #define CPUID_MSR 0x00000020 123 #define CPUID_PAE 0x00000040 124 #define CPUID_MCE 0x00000080 125 #define CPUID_CX8 0x00000100 126 #define CPUID_APIC 0x00000200 127 #define CPUID_B10 0x00000400 128 #define CPUID_SEP 0x00000800 129 #define CPUID_MTRR 0x00001000 130 #define CPUID_PGE 0x00002000 131 #define CPUID_MCA 0x00004000 132 #define CPUID_CMOV 0x00008000 133 #define CPUID_PAT 0x00010000 134 #define CPUID_PSE36 0x00020000 135 #define CPUID_PSN 0x00040000 136 #define CPUID_CLFSH 0x00080000 137 #define CPUID_B20 0x00100000 138 #define CPUID_DS 0x00200000 139 #define CPUID_ACPI 0x00400000 140 #define CPUID_MMX 0x00800000 141 #define CPUID_FXSR 0x01000000 142 #define CPUID_SSE 0x02000000 143 #define CPUID_XMM 0x02000000 144 #define CPUID_SSE2 0x04000000 145 #define CPUID_SS 0x08000000 146 #define CPUID_HTT 0x10000000 147 #define CPUID_TM 0x20000000 148 #define CPUID_IA64 0x40000000 149 #define CPUID_PBE 0x80000000 150 151 #define CPUID2_SSE3 0x00000001 152 #define CPUID2_PCLMULQDQ 0x00000002 153 #define CPUID2_DTES64 0x00000004 154 #define CPUID2_MON 0x00000008 155 #define CPUID2_DS_CPL 0x00000010 156 #define CPUID2_VMX 0x00000020 157 #define CPUID2_SMX 0x00000040 158 #define CPUID2_EST 0x00000080 159 #define CPUID2_TM2 0x00000100 160 #define CPUID2_SSSE3 0x00000200 161 #define CPUID2_CNXTID 0x00000400 162 #define CPUID2_SDBG 0x00000800 163 #define CPUID2_FMA 0x00001000 164 #define CPUID2_CX16 0x00002000 165 #define CPUID2_XTPR 0x00004000 166 #define CPUID2_PDCM 0x00008000 167 #define CPUID2_PCID 0x00020000 168 #define CPUID2_DCA 0x00040000 169 #define CPUID2_SSE41 0x00080000 170 #define CPUID2_SSE42 0x00100000 171 #define CPUID2_X2APIC 0x00200000 172 #define CPUID2_MOVBE 0x00400000 173 #define CPUID2_POPCNT 0x00800000 174 #define CPUID2_TSCDLT 0x01000000 175 #define CPUID2_AESNI 0x02000000 176 #define CPUID2_XSAVE 0x04000000 177 #define CPUID2_OSXSAVE 0x08000000 178 #define CPUID2_AVX 0x10000000 179 #define CPUID2_F16C 0x20000000 180 #define CPUID2_RDRAND 0x40000000 181 #define CPUID2_HV 0x80000000 182 183 /* 184 * Important bits in the Thermal and Power Management flags 185 * CPUID.6 EAX and ECX. 186 */ 187 #define CPUTPM1_SENSOR 0x00000001 188 #define CPUTPM1_TURBO 0x00000002 189 #define CPUTPM1_ARAT 0x00000004 190 #define CPUTPM1_HWP 0x00000080 191 #define CPUTPM1_HWP_NOTIFICATION 0x00000100 192 #define CPUTPM1_HWP_ACTIVITY_WINDOW 0x00000200 193 #define CPUTPM1_HWP_PERF_PREF 0x00000400 194 #define CPUTPM1_HWP_PKG 0x00000800 195 #define CPUTPM1_HWP_FLEXIBLE 0x00020000 196 #define CPUTPM2_EFFREQ 0x00000001 197 198 /* 199 * Important bits in the AMD extended cpuid flags 200 */ 201 #define AMDID_SYSCALL 0x00000800 202 #define AMDID_MP 0x00080000 203 #define AMDID_NX 0x00100000 204 #define AMDID_EXT_MMX 0x00400000 205 #define AMDID_FFXSR 0x02000000 206 #define AMDID_PAGE1GB 0x04000000 207 #define AMDID_RDTSCP 0x08000000 208 #define AMDID_LM 0x20000000 209 #define AMDID_EXT_3DNOW 0x40000000 210 #define AMDID_3DNOW 0x80000000 211 212 #define AMDID2_LAHF 0x00000001 213 #define AMDID2_CMP 0x00000002 214 #define AMDID2_SVM 0x00000004 215 #define AMDID2_EXT_APIC 0x00000008 216 #define AMDID2_CR8 0x00000010 217 #define AMDID2_ABM 0x00000020 218 #define AMDID2_SSE4A 0x00000040 219 #define AMDID2_MAS 0x00000080 220 #define AMDID2_PREFETCH 0x00000100 221 #define AMDID2_OSVW 0x00000200 222 #define AMDID2_IBS 0x00000400 223 #define AMDID2_XOP 0x00000800 224 #define AMDID2_SKINIT 0x00001000 225 #define AMDID2_WDT 0x00002000 226 #define AMDID2_LWP 0x00008000 227 #define AMDID2_FMA4 0x00010000 228 #define AMDID2_TCE 0x00020000 229 #define AMDID2_NODE_ID 0x00080000 230 #define AMDID2_TBM 0x00200000 231 #define AMDID2_TOPOLOGY 0x00400000 232 #define AMDID2_PCXC 0x00800000 233 #define AMDID2_PNXC 0x01000000 234 #define AMDID2_DBE 0x04000000 235 #define AMDID2_PTSC 0x08000000 236 #define AMDID2_PTSCEL2I 0x10000000 237 #define AMDID2_MWAITX 0x20000000 238 239 /* 240 * CPUID instruction 1 eax info 241 */ 242 #define CPUID_STEPPING 0x0000000f 243 #define CPUID_MODEL 0x000000f0 244 #define CPUID_FAMILY 0x00000f00 245 #define CPUID_EXT_MODEL 0x000f0000 246 #define CPUID_EXT_FAMILY 0x0ff00000 247 #ifdef __i386__ 248 #define CPUID_TO_MODEL(id) \ 249 ((((id) & CPUID_MODEL) >> 4) | \ 250 ((((id) & CPUID_FAMILY) >= 0x600) ? \ 251 (((id) & CPUID_EXT_MODEL) >> 12) : 0)) 252 #define CPUID_TO_FAMILY(id) \ 253 ((((id) & CPUID_FAMILY) >> 8) + \ 254 ((((id) & CPUID_FAMILY) == 0xf00) ? \ 255 (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) 256 #else 257 #define CPUID_TO_MODEL(id) \ 258 ((((id) & CPUID_MODEL) >> 4) | \ 259 (((id) & CPUID_EXT_MODEL) >> 12)) 260 #define CPUID_TO_FAMILY(id) \ 261 ((((id) & CPUID_FAMILY) >> 8) + \ 262 (((id) & CPUID_EXT_FAMILY) >> 20)) 263 #endif 264 265 /* 266 * CPUID instruction 1 ebx info 267 */ 268 #define CPUID_BRAND_INDEX 0x000000ff 269 #define CPUID_CLFUSH_SIZE 0x0000ff00 270 #define CPUID_HTT_CORES 0x00ff0000 271 #define CPUID_LOCAL_APIC_ID 0xff000000 272 273 /* 274 * CPUID instruction 5 info 275 */ 276 #define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */ 277 #define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */ 278 #define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */ 279 #define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */ 280 281 /* 282 * MWAIT cpu power states. Lower 4 bits are sub-states. 283 */ 284 #define MWAIT_C0 0xf0 285 #define MWAIT_C1 0x00 286 #define MWAIT_C2 0x10 287 #define MWAIT_C3 0x20 288 #define MWAIT_C4 0x30 289 290 /* 291 * MWAIT extensions. 292 */ 293 /* Interrupt breaks MWAIT even when masked. */ 294 #define MWAIT_INTRBREAK 0x00000001 295 296 /* 297 * CPUID instruction 6 ecx info 298 */ 299 #define CPUID_PERF_STAT 0x00000001 300 #define CPUID_PERF_BIAS 0x00000008 301 302 /* 303 * CPUID instruction 0xb ebx info. 304 */ 305 #define CPUID_TYPE_INVAL 0 306 #define CPUID_TYPE_SMT 1 307 #define CPUID_TYPE_CORE 2 308 309 /* 310 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1 311 */ 312 #define CPUID_EXTSTATE_XSAVEOPT 0x00000001 313 #define CPUID_EXTSTATE_XSAVEC 0x00000002 314 #define CPUID_EXTSTATE_XINUSE 0x00000004 315 #define CPUID_EXTSTATE_XSAVES 0x00000008 316 317 /* 318 * AMD extended function 8000_0007h edx info 319 */ 320 #define AMDPM_TS 0x00000001 321 #define AMDPM_FID 0x00000002 322 #define AMDPM_VID 0x00000004 323 #define AMDPM_TTP 0x00000008 324 #define AMDPM_TM 0x00000010 325 #define AMDPM_STC 0x00000020 326 #define AMDPM_100MHZ_STEPS 0x00000040 327 #define AMDPM_HW_PSTATE 0x00000080 328 #define AMDPM_TSC_INVARIANT 0x00000100 329 #define AMDPM_CPB 0x00000200 330 331 /* 332 * AMD extended function 8000_0008h ebx info (amd_extended_feature_extensions) 333 */ 334 #define AMDFEID_CLZERO 0x00000001 335 #define AMDFEID_IRPERF 0x00000002 336 #define AMDFEID_XSAVEERPTR 0x00000004 337 338 /* 339 * AMD extended function 8000_0008h ecx info 340 */ 341 #define AMDID_CMP_CORES 0x000000ff 342 #define AMDID_COREID_SIZE 0x0000f000 343 #define AMDID_COREID_SIZE_SHIFT 12 344 345 /* 346 * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info 347 */ 348 #define CPUID_STDEXT_FSGSBASE 0x00000001 349 #define CPUID_STDEXT_TSC_ADJUST 0x00000002 350 #define CPUID_STDEXT_SGX 0x00000004 351 #define CPUID_STDEXT_BMI1 0x00000008 352 #define CPUID_STDEXT_HLE 0x00000010 353 #define CPUID_STDEXT_AVX2 0x00000020 354 #define CPUID_STDEXT_FDP_EXC 0x00000040 355 #define CPUID_STDEXT_SMEP 0x00000080 356 #define CPUID_STDEXT_BMI2 0x00000100 357 #define CPUID_STDEXT_ERMS 0x00000200 358 #define CPUID_STDEXT_INVPCID 0x00000400 359 #define CPUID_STDEXT_RTM 0x00000800 360 #define CPUID_STDEXT_PQM 0x00001000 361 #define CPUID_STDEXT_NFPUSG 0x00002000 362 #define CPUID_STDEXT_MPX 0x00004000 363 #define CPUID_STDEXT_PQE 0x00008000 364 #define CPUID_STDEXT_AVX512F 0x00010000 365 #define CPUID_STDEXT_AVX512DQ 0x00020000 366 #define CPUID_STDEXT_RDSEED 0x00040000 367 #define CPUID_STDEXT_ADX 0x00080000 368 #define CPUID_STDEXT_SMAP 0x00100000 369 #define CPUID_STDEXT_AVX512IFMA 0x00200000 370 #define CPUID_STDEXT_PCOMMIT 0x00400000 371 #define CPUID_STDEXT_CLFLUSHOPT 0x00800000 372 #define CPUID_STDEXT_CLWB 0x01000000 373 #define CPUID_STDEXT_PROCTRACE 0x02000000 374 #define CPUID_STDEXT_AVX512PF 0x04000000 375 #define CPUID_STDEXT_AVX512ER 0x08000000 376 #define CPUID_STDEXT_AVX512CD 0x10000000 377 #define CPUID_STDEXT_SHA 0x20000000 378 #define CPUID_STDEXT_AVX512BW 0x40000000 379 #define CPUID_STDEXT_AVX512VL 0x80000000 380 381 /* 382 * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info 383 */ 384 #define CPUID_STDEXT2_PREFETCHWT1 0x00000001 385 #define CPUID_STDEXT2_AVX512VBMI 0x00000002 386 #define CPUID_STDEXT2_UMIP 0x00000004 387 #define CPUID_STDEXT2_PKU 0x00000008 388 #define CPUID_STDEXT2_OSPKE 0x00000010 389 #define CPUID_STDEXT2_WAITPKG 0x00000020 390 #define CPUID_STDEXT2_AVX512VBMI2 0x00000040 391 #define CPUID_STDEXT2_GFNI 0x00000100 392 #define CPUID_STDEXT2_VAES 0x00000200 393 #define CPUID_STDEXT2_VPCLMULQDQ 0x00000400 394 #define CPUID_STDEXT2_AVX512VNNI 0x00000800 395 #define CPUID_STDEXT2_AVX512BITALG 0x00001000 396 #define CPUID_STDEXT2_AVX512VPOPCNTDQ 0x00004000 397 #define CPUID_STDEXT2_RDPID 0x00400000 398 #define CPUID_STDEXT2_CLDEMOTE 0x02000000 399 #define CPUID_STDEXT2_MOVDIRI 0x08000000 400 #define CPUID_STDEXT2_MOVDIRI64B 0x10000000 401 #define CPUID_STDEXT2_ENQCMD 0x20000000 402 #define CPUID_STDEXT2_SGXLC 0x40000000 403 404 /* 405 * CPUID instruction 7 Structured Extended Features, leaf 0 edx info 406 */ 407 #define CPUID_STDEXT3_AVX5124VNNIW 0x00000004 408 #define CPUID_STDEXT3_AVX5124FMAPS 0x00000008 409 #define CPUID_STDEXT3_AVX512VP2INTERSECT 0x00000100 410 #define CPUID_STDEXT3_MCUOPT 0x00000200 411 #define CPUID_STDEXT3_MD_CLEAR 0x00000400 412 #define CPUID_STDEXT3_TSXFA 0x00002000 413 #define CPUID_STDEXT3_PCONFIG 0x00040000 414 #define CPUID_STDEXT3_IBPB 0x04000000 415 #define CPUID_STDEXT3_STIBP 0x08000000 416 #define CPUID_STDEXT3_L1D_FLUSH 0x10000000 417 #define CPUID_STDEXT3_ARCH_CAP 0x20000000 418 #define CPUID_STDEXT3_CORE_CAP 0x40000000 419 #define CPUID_STDEXT3_SSBD 0x80000000 420 421 /* MSR IA32_ARCH_CAP(ABILITIES) bits */ 422 #define IA32_ARCH_CAP_RDCL_NO 0x00000001 423 #define IA32_ARCH_CAP_IBRS_ALL 0x00000002 424 #define IA32_ARCH_CAP_RSBA 0x00000004 425 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x00000008 426 #define IA32_ARCH_CAP_SSB_NO 0x00000010 427 #define IA32_ARCH_CAP_MDS_NO 0x00000020 428 #define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x00000040 429 #define IA32_ARCH_CAP_TSX_CTRL 0x00000080 430 #define IA32_ARCH_CAP_TAA_NO 0x00000100 431 432 /* MSR IA32_TSX_CTRL bits */ 433 #define IA32_TSX_CTRL_RTM_DISABLE 0x00000001 434 #define IA32_TSX_CTRL_TSX_CPUID_CLEAR 0x00000002 435 436 /* 437 * CPUID manufacturers identifiers 438 */ 439 #define AMD_VENDOR_ID "AuthenticAMD" 440 #define CENTAUR_VENDOR_ID "CentaurHauls" 441 #define CYRIX_VENDOR_ID "CyrixInstead" 442 #define INTEL_VENDOR_ID "GenuineIntel" 443 #define NEXGEN_VENDOR_ID "NexGenDriven" 444 #define NSC_VENDOR_ID "Geode by NSC" 445 #define RISE_VENDOR_ID "RiseRiseRise" 446 #define SIS_VENDOR_ID "SiS SiS SiS " 447 #define TRANSMETA_VENDOR_ID "GenuineTMx86" 448 #define UMC_VENDOR_ID "UMC UMC UMC " 449 450 /* 451 * Model-specific registers for the i386 family 452 */ 453 #define MSR_P5_MC_ADDR 0x000 454 #define MSR_P5_MC_TYPE 0x001 455 #define MSR_TSC 0x010 456 #define MSR_P5_CESR 0x011 457 #define MSR_P5_CTR0 0x012 458 #define MSR_P5_CTR1 0x013 459 #define MSR_IA32_PLATFORM_ID 0x017 460 #define MSR_APICBASE 0x01b 461 #define MSR_EBL_CR_POWERON 0x02a 462 #define MSR_TEST_CTL 0x033 463 #define MSR_IA32_FEATURE_CONTROL 0x03a 464 #define MSR_IA32_SPEC_CTRL 0x048 465 #define MSR_IA32_PRED_CMD 0x049 466 #define MSR_BIOS_UPDT_TRIG 0x079 467 #define MSR_BBL_CR_D0 0x088 468 #define MSR_BBL_CR_D1 0x089 469 #define MSR_BBL_CR_D2 0x08a 470 #define MSR_BIOS_SIGN 0x08b 471 #define MSR_PERFCTR0 0x0c1 472 #define MSR_PERFCTR1 0x0c2 473 #define MSR_PLATFORM_INFO 0x0ce 474 #define MSR_MPERF 0x0e7 475 #define MSR_APERF 0x0e8 476 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 477 #define MSR_MTRRcap 0x0fe 478 #define MSR_IA32_ARCH_CAP 0x10a 479 #define MSR_IA32_FLUSH_CMD 0x10b 480 #define MSR_TSX_FORCE_ABORT 0x10f 481 #define MSR_BBL_CR_ADDR 0x116 482 #define MSR_BBL_CR_DECC 0x118 483 #define MSR_BBL_CR_CTL 0x119 484 #define MSR_BBL_CR_TRIG 0x11a 485 #define MSR_BBL_CR_BUSY 0x11b 486 #define MSR_BBL_CR_CTL3 0x11e 487 #define MSR_IA32_TSX_CTRL 0x122 488 #define MSR_IA32_MCU_OPT_CTRL 0x123 489 #define MSR_SYSENTER_CS_MSR 0x174 490 #define MSR_SYSENTER_ESP_MSR 0x175 491 #define MSR_SYSENTER_EIP_MSR 0x176 492 #define MSR_MCG_CAP 0x179 493 #define MSR_MCG_STATUS 0x17a 494 #define MSR_MCG_CTL 0x17b 495 #define MSR_EVNTSEL0 0x186 496 #define MSR_EVNTSEL1 0x187 497 #define MSR_THERM_CONTROL 0x19a 498 #define MSR_THERM_INTERRUPT 0x19b 499 #define MSR_THERM_STATUS 0x19c 500 #define MSR_IA32_MISC_ENABLE 0x1a0 501 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2 502 #define MSR_TURBO_RATIO_LIMIT 0x1ad 503 #define MSR_TURBO_RATIO_LIMIT1 0x1ae 504 #define MSR_DEBUGCTLMSR 0x1d9 505 #define MSR_LASTBRANCHFROMIP 0x1db 506 #define MSR_LASTBRANCHTOIP 0x1dc 507 #define MSR_LASTINTFROMIP 0x1dd 508 #define MSR_LASTINTTOIP 0x1de 509 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 510 #define MSR_MTRRVarBase 0x200 511 #define MSR_MTRR64kBase 0x250 512 #define MSR_MTRR16kBase 0x258 513 #define MSR_MTRR4kBase 0x268 514 #define MSR_PAT 0x277 515 #define MSR_MC0_CTL2 0x280 516 #define MSR_MTRRdefType 0x2ff 517 #define MSR_MC0_CTL 0x400 518 #define MSR_MC0_STATUS 0x401 519 #define MSR_MC0_ADDR 0x402 520 #define MSR_MC0_MISC 0x403 521 #define MSR_MC1_CTL 0x404 522 #define MSR_MC1_STATUS 0x405 523 #define MSR_MC1_ADDR 0x406 524 #define MSR_MC1_MISC 0x407 525 #define MSR_MC2_CTL 0x408 526 #define MSR_MC2_STATUS 0x409 527 #define MSR_MC2_ADDR 0x40a 528 #define MSR_MC2_MISC 0x40b 529 #define MSR_MC3_CTL 0x40c 530 #define MSR_MC3_STATUS 0x40d 531 #define MSR_MC3_ADDR 0x40e 532 #define MSR_MC3_MISC 0x40f 533 #define MSR_MC4_CTL 0x410 534 #define MSR_MC4_STATUS 0x411 535 #define MSR_MC4_ADDR 0x412 536 #define MSR_MC4_MISC 0x413 537 #define MSR_RAPL_POWER_UNIT 0x606 538 #define MSR_PKG_ENERGY_STATUS 0x611 539 #define MSR_DRAM_ENERGY_STATUS 0x619 540 #define MSR_PP0_ENERGY_STATUS 0x639 541 #define MSR_PP1_ENERGY_STATUS 0x641 542 #define MSR_PPERF 0x64e 543 #define MSR_TSC_DEADLINE 0x6e0 /* Writes are not serializing */ 544 #define MSR_IA32_PM_ENABLE 0x770 545 #define MSR_IA32_HWP_CAPABILITIES 0x771 546 #define MSR_IA32_HWP_REQUEST_PKG 0x772 547 #define MSR_IA32_HWP_INTERRUPT 0x773 548 #define MSR_IA32_HWP_REQUEST 0x774 549 #define MSR_IA32_HWP_STATUS 0x777 550 551 /* 552 * VMX MSRs 553 */ 554 #define MSR_VMX_BASIC 0x480 555 #define MSR_VMX_PINBASED_CTLS 0x481 556 #define MSR_VMX_PROCBASED_CTLS 0x482 557 #define MSR_VMX_EXIT_CTLS 0x483 558 #define MSR_VMX_ENTRY_CTLS 0x484 559 #define MSR_VMX_CR0_FIXED0 0x486 560 #define MSR_VMX_CR0_FIXED1 0x487 561 #define MSR_VMX_CR4_FIXED0 0x488 562 #define MSR_VMX_CR4_FIXED1 0x489 563 #define MSR_VMX_PROCBASED_CTLS2 0x48b 564 #define MSR_VMX_EPT_VPID_CAP 0x48c 565 #define MSR_VMX_TRUE_PINBASED_CTLS 0x48d 566 #define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e 567 #define MSR_VMX_TRUE_EXIT_CTLS 0x48f 568 #define MSR_VMX_TRUE_ENTRY_CTLS 0x490 569 570 /* 571 * X2APIC MSRs. 572 * Writes are not serializing. 573 */ 574 #define MSR_APIC_000 0x800 575 #define MSR_APIC_ID 0x802 576 #define MSR_APIC_VERSION 0x803 577 #define MSR_APIC_TPR 0x808 578 #define MSR_APIC_EOI 0x80b 579 #define MSR_APIC_LDR 0x80d 580 #define MSR_APIC_SVR 0x80f 581 #define MSR_APIC_ISR0 0x810 582 #define MSR_APIC_ISR1 0x811 583 #define MSR_APIC_ISR2 0x812 584 #define MSR_APIC_ISR3 0x813 585 #define MSR_APIC_ISR4 0x814 586 #define MSR_APIC_ISR5 0x815 587 #define MSR_APIC_ISR6 0x816 588 #define MSR_APIC_ISR7 0x817 589 #define MSR_APIC_TMR0 0x818 590 #define MSR_APIC_IRR0 0x820 591 #define MSR_APIC_ESR 0x828 592 #define MSR_APIC_LVT_CMCI 0x82F 593 #define MSR_APIC_ICR 0x830 594 #define MSR_APIC_LVT_TIMER 0x832 595 #define MSR_APIC_LVT_THERMAL 0x833 596 #define MSR_APIC_LVT_PCINT 0x834 597 #define MSR_APIC_LVT_LINT0 0x835 598 #define MSR_APIC_LVT_LINT1 0x836 599 #define MSR_APIC_LVT_ERROR 0x837 600 #define MSR_APIC_ICR_TIMER 0x838 601 #define MSR_APIC_CCR_TIMER 0x839 602 #define MSR_APIC_DCR_TIMER 0x83e 603 #define MSR_APIC_SELF_IPI 0x83f 604 605 #define MSR_IA32_XSS 0xda0 606 607 /* 608 * Constants related to MSR's. 609 */ 610 #define APICBASE_RESERVED 0x000002ff 611 #define APICBASE_BSP 0x00000100 612 #define APICBASE_X2APIC 0x00000400 613 #define APICBASE_ENABLED 0x00000800 614 #define APICBASE_ADDRESS 0xfffff000 615 616 /* MSR_IA32_FEATURE_CONTROL related */ 617 #define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */ 618 #define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */ 619 #define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */ 620 621 /* MSR IA32_MISC_ENABLE */ 622 #define IA32_MISC_EN_FASTSTR 0x0000000000000001ULL 623 #define IA32_MISC_EN_ATCCE 0x0000000000000008ULL 624 #define IA32_MISC_EN_PERFMON 0x0000000000000080ULL 625 #define IA32_MISC_EN_PEBSU 0x0000000000001000ULL 626 #define IA32_MISC_EN_ESSTE 0x0000000000010000ULL 627 #define IA32_MISC_EN_MONE 0x0000000000040000ULL 628 #define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL 629 #define IA32_MISC_EN_xTPRD 0x0000000000800000ULL 630 #define IA32_MISC_EN_XDD 0x0000000400000000ULL 631 632 /* 633 * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel' 634 * document 336996-001 Speculative Execution Side Channel Mitigations. 635 */ 636 /* MSR IA32_SPEC_CTRL */ 637 #define IA32_SPEC_CTRL_IBRS 0x00000001 638 #define IA32_SPEC_CTRL_STIBP 0x00000002 639 #define IA32_SPEC_CTRL_SSBD 0x00000004 640 641 /* MSR IA32_PRED_CMD */ 642 #define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL 643 644 /* MSR IA32_FLUSH_CMD */ 645 #define IA32_FLUSH_CMD_L1D 0x00000001 646 647 /* MSR IA32_MCU_OPT_CTRL */ 648 #define IA32_RNGDS_MITG_DIS 0x00000001 649 650 /* MSR IA32_HWP_CAPABILITIES */ 651 #define IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(x) (((x) >> 0) & 0xff) 652 #define IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(x) (((x) >> 8) & 0xff) 653 #define IA32_HWP_CAPABILITIES_EFFICIENT_PERFORMANCE(x) (((x) >> 16) & 0xff) 654 #define IA32_HWP_CAPABILITIES_LOWEST_PERFORMANCE(x) (((x) >> 24) & 0xff) 655 656 /* MSR IA32_HWP_REQUEST */ 657 #define IA32_HWP_REQUEST_MINIMUM_VALID (1ULL << 63) 658 #define IA32_HWP_REQUEST_MAXIMUM_VALID (1ULL << 62) 659 #define IA32_HWP_REQUEST_DESIRED_VALID (1ULL << 61) 660 #define IA32_HWP_REQUEST_EPP_VALID (1ULL << 60) 661 #define IA32_HWP_REQUEST_ACTIVITY_WINDOW_VALID (1ULL << 59) 662 #define IA32_HWP_REQUEST_PACKAGE_CONTROL (1ULL << 42) 663 #define IA32_HWP_ACTIVITY_WINDOW (0x3ffULL << 32) 664 #define IA32_HWP_REQUEST_ENERGY_PERFORMANCE_PREFERENCE (0xffULL << 24) 665 #define IA32_HWP_DESIRED_PERFORMANCE (0xffULL << 16) 666 #define IA32_HWP_REQUEST_MAXIMUM_PERFORMANCE (0xffULL << 8) 667 #define IA32_HWP_MINIMUM_PERFORMANCE (0xffULL << 0) 668 669 /* 670 * PAT modes. 671 */ 672 #define PAT_UNCACHEABLE 0x00 673 #define PAT_WRITE_COMBINING 0x01 674 #define PAT_WRITE_THROUGH 0x04 675 #define PAT_WRITE_PROTECTED 0x05 676 #define PAT_WRITE_BACK 0x06 677 #define PAT_UNCACHED 0x07 678 #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 679 #define PAT_MASK(i) PAT_VALUE(i, 0xff) 680 681 /* 682 * Constants related to MTRRs 683 */ 684 #define MTRR_UNCACHEABLE 0x00 685 #define MTRR_WRITE_COMBINING 0x01 686 #define MTRR_WRITE_THROUGH 0x04 687 #define MTRR_WRITE_PROTECTED 0x05 688 #define MTRR_WRITE_BACK 0x06 689 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 690 #define MTRR_N16K 16 691 #define MTRR_N4K 64 692 #define MTRR_CAP_WC 0x0000000000000400 693 #define MTRR_CAP_FIXED 0x0000000000000100 694 #define MTRR_CAP_VCNT 0x00000000000000ff 695 #define MTRR_DEF_ENABLE 0x0000000000000800 696 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 697 #define MTRR_DEF_TYPE 0x00000000000000ff 698 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 699 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff 700 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 701 #define MTRR_PHYSMASK_VALID 0x0000000000000800 702 703 /* 704 * Cyrix configuration registers, accessible as IO ports. 705 */ 706 #define CCR0 0xc0 /* Configuration control register 0 */ 707 #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 708 non-cacheable */ 709 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 710 #define CCR0_A20M 0x04 /* Enables A20M# input pin */ 711 #define CCR0_KEN 0x08 /* Enables KEN# input pin */ 712 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 713 #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 714 state */ 715 #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 716 assoc */ 717 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 718 719 #define CCR1 0xc1 /* Configuration control register 1 */ 720 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 721 #define CCR1_SMI 0x02 /* Enables SMM pins */ 722 #define CCR1_SMAC 0x04 /* System management memory access */ 723 #define CCR1_MMAC 0x08 /* Main memory access */ 724 #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 725 #define CCR1_SM3 0x80 /* SMM address space address region 3 */ 726 727 #define CCR2 0xc2 728 #define CCR2_WB 0x02 /* Enables WB cache interface pins */ 729 #define CCR2_SADS 0x02 /* Slow ADS */ 730 #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 731 #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 732 #define CCR2_WT1 0x10 /* WT region 1 */ 733 #define CCR2_WPR1 0x10 /* Write-protect region 1 */ 734 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering 735 hold state. */ 736 #define CCR2_BWRT 0x40 /* Enables burst write cycles */ 737 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 738 739 #define CCR3 0xc3 740 #define CCR3_SMILOCK 0x01 /* SMM register lock */ 741 #define CCR3_NMI 0x02 /* Enables NMI during SMM */ 742 #define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 743 #define CCR3_SMMMODE 0x08 /* SMM Mode */ 744 #define CCR3_MAPEN0 0x10 /* Enables Map0 */ 745 #define CCR3_MAPEN1 0x20 /* Enables Map1 */ 746 #define CCR3_MAPEN2 0x40 /* Enables Map2 */ 747 #define CCR3_MAPEN3 0x80 /* Enables Map3 */ 748 749 #define CCR4 0xe8 750 #define CCR4_IOMASK 0x07 751 #define CCR4_MEM 0x08 /* Enables momory bypassing */ 752 #define CCR4_DTE 0x10 /* Enables directory table entry cache */ 753 #define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 754 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 755 756 #define CCR5 0xe9 757 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 758 #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 759 #define CCR5_LBR1 0x10 /* Local bus region 1 */ 760 #define CCR5_ARREN 0x20 /* Enables ARR region */ 761 762 #define CCR6 0xea 763 764 #define CCR7 0xeb 765 766 /* Performance Control Register (5x86 only). */ 767 #define PCR0 0x20 768 #define PCR0_RSTK 0x01 /* Enables return stack */ 769 #define PCR0_BTB 0x02 /* Enables branch target buffer */ 770 #define PCR0_LOOP 0x04 /* Enables loop */ 771 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 772 serialize pipe. */ 773 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 774 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 775 #define PCR0_LSSER 0x80 /* Disable reorder */ 776 777 /* Device Identification Registers */ 778 #define DIR0 0xfe 779 #define DIR1 0xff 780 781 /* 782 * Machine Check register constants. 783 */ 784 #define MCG_CAP_COUNT 0x000000ff 785 #define MCG_CAP_CTL_P 0x00000100 786 #define MCG_CAP_EXT_P 0x00000200 787 #define MCG_CAP_CMCI_P 0x00000400 788 #define MCG_CAP_TES_P 0x00000800 789 #define MCG_CAP_EXT_CNT 0x00ff0000 790 #define MCG_CAP_SER_P 0x01000000 791 #define MCG_STATUS_RIPV 0x00000001 792 #define MCG_STATUS_EIPV 0x00000002 793 #define MCG_STATUS_MCIP 0x00000004 794 #define MCG_CTL_ENABLE 0xffffffffffffffff 795 #define MCG_CTL_DISABLE 0x0000000000000000 796 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 797 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 798 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 799 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 800 #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 801 #define MC_STATUS_MCA_ERROR 0x000000000000ffff 802 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 803 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000 804 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ 805 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ 806 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ 807 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ 808 #define MC_STATUS_PCC 0x0200000000000000 809 #define MC_STATUS_ADDRV 0x0400000000000000 810 #define MC_STATUS_MISCV 0x0800000000000000 811 #define MC_STATUS_EN 0x1000000000000000 812 #define MC_STATUS_UC 0x2000000000000000 813 #define MC_STATUS_OVER 0x4000000000000000 814 #define MC_STATUS_VAL 0x8000000000000000 815 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ 816 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ 817 #define MC_CTL2_THRESHOLD 0x0000000000007fff 818 #define MC_CTL2_CMCI_EN 0x0000000040000000 819 #define MC_AMDNB_BANK 4 820 #define MC_MISC_AMDNB_VAL 0x8000000000000000 /* Counter presence valid */ 821 #define MC_MISC_AMDNB_CNTP 0x4000000000000000 /* Counter present */ 822 #define MC_MISC_AMDNB_LOCK 0x2000000000000000 /* Register locked */ 823 #define MC_MISC_AMDNB_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */ 824 #define MC_MISC_AMDNB_LVT_SHIFT 52 825 #define MC_MISC_AMDNB_CNTEN 0x0008000000000000 /* Counter enabled */ 826 #define MC_MISC_AMDNB_INT_MASK 0x0006000000000000 /* Interrupt type */ 827 #define MC_MISC_AMDNB_INT_LVT 0x0002000000000000 /* Interrupt via Extended LVT */ 828 #define MC_MISC_AMDNB_INT_SMI 0x0004000000000000 /* SMI */ 829 #define MC_MISC_AMDNB_OVERFLOW 0x0001000000000000 /* Counter overflow */ 830 #define MC_MISC_AMDNB_CNT_MASK 0x00000fff00000000 /* Counter value */ 831 #define MC_MISC_AMDNB_CNT_SHIFT 32 832 #define MC_MISC_AMDNB_CNT_MAX 0xfff 833 #define MC_MISC_AMDNB_PTR_MASK 0x00000000ff000000 /* Pointer to additional registers */ 834 #define MC_MISC_AMDNB_PTR_SHIFT 24 835 836 /* 837 * The following four 3-byte registers control the non-cacheable regions. 838 * These registers must be written as three separate bytes. 839 * 840 * NCRx+0: A31-A24 of starting address 841 * NCRx+1: A23-A16 of starting address 842 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 843 * 844 * The non-cacheable region's starting address must be aligned to the 845 * size indicated by the NCR_SIZE_xx field. 846 */ 847 #define NCR1 0xc4 848 #define NCR2 0xc7 849 #define NCR3 0xca 850 #define NCR4 0xcd 851 852 #define NCR_SIZE_0K 0 853 #define NCR_SIZE_4K 1 854 #define NCR_SIZE_8K 2 855 #define NCR_SIZE_16K 3 856 #define NCR_SIZE_32K 4 857 #define NCR_SIZE_64K 5 858 #define NCR_SIZE_128K 6 859 #define NCR_SIZE_256K 7 860 #define NCR_SIZE_512K 8 861 #define NCR_SIZE_1M 9 862 #define NCR_SIZE_2M 10 863 #define NCR_SIZE_4M 11 864 #define NCR_SIZE_8M 12 865 #define NCR_SIZE_16M 13 866 #define NCR_SIZE_32M 14 867 #define NCR_SIZE_4G 15 868 869 /* 870 * The address region registers are used to specify the location and 871 * size for the eight address regions. 872 * 873 * ARRx + 0: A31-A24 of start address 874 * ARRx + 1: A23-A16 of start address 875 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 876 */ 877 #define ARR0 0xc4 878 #define ARR1 0xc7 879 #define ARR2 0xca 880 #define ARR3 0xcd 881 #define ARR4 0xd0 882 #define ARR5 0xd3 883 #define ARR6 0xd6 884 #define ARR7 0xd9 885 886 #define ARR_SIZE_0K 0 887 #define ARR_SIZE_4K 1 888 #define ARR_SIZE_8K 2 889 #define ARR_SIZE_16K 3 890 #define ARR_SIZE_32K 4 891 #define ARR_SIZE_64K 5 892 #define ARR_SIZE_128K 6 893 #define ARR_SIZE_256K 7 894 #define ARR_SIZE_512K 8 895 #define ARR_SIZE_1M 9 896 #define ARR_SIZE_2M 10 897 #define ARR_SIZE_4M 11 898 #define ARR_SIZE_8M 12 899 #define ARR_SIZE_16M 13 900 #define ARR_SIZE_32M 14 901 #define ARR_SIZE_4G 15 902 903 /* 904 * The region control registers specify the attributes associated with 905 * the ARRx addres regions. 906 */ 907 #define RCR0 0xdc 908 #define RCR1 0xdd 909 #define RCR2 0xde 910 #define RCR3 0xdf 911 #define RCR4 0xe0 912 #define RCR5 0xe1 913 #define RCR6 0xe2 914 #define RCR7 0xe3 915 916 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 917 #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 918 #define RCR_WWO 0x02 /* Weak write ordering. */ 919 #define RCR_WL 0x04 /* Weak locking. */ 920 #define RCR_WG 0x08 /* Write gathering. */ 921 #define RCR_WT 0x10 /* Write-through. */ 922 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 923 924 /* AMD Write Allocate Top-Of-Memory and Control Register */ 925 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 926 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 927 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 928 929 /* AMD64 MSR's */ 930 #define MSR_EFER 0xc0000080 /* extended features */ 931 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 932 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 933 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 934 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 935 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 936 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 937 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 938 #define MSR_TSC_AUX 0xc0000103 939 #define MSR_PERFEVSEL0 0xc0010000 940 #define MSR_PERFEVSEL1 0xc0010001 941 #define MSR_PERFEVSEL2 0xc0010002 942 #define MSR_PERFEVSEL3 0xc0010003 943 #define MSR_K7_PERFCTR0 0xc0010004 944 #define MSR_K7_PERFCTR1 0xc0010005 945 #define MSR_K7_PERFCTR2 0xc0010006 946 #define MSR_K7_PERFCTR3 0xc0010007 947 #define MSR_SYSCFG 0xc0010010 948 #define MSR_HWCR 0xc0010015 949 #define MSR_IORRBASE0 0xc0010016 950 #define MSR_IORRMASK0 0xc0010017 951 #define MSR_IORRBASE1 0xc0010018 952 #define MSR_IORRMASK1 0xc0010019 953 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 954 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 955 #define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */ 956 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 957 #define MSR_MC0_CTL_MASK 0xc0010044 958 #define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */ 959 #define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */ 960 #define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */ 961 #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */ 962 #define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */ 963 #define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */ 964 #define MSR_VM_CR 0xc0010114 /* SVM: feature control */ 965 #define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */ 966 #define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */ 967 #define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */ 968 #define MSR_LS_CFG 0xc0011020 969 #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */ 970 971 /* MSR_VM_CR related */ 972 #define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */ 973 974 /* VIA ACE crypto featureset: for via_feature_rng */ 975 #define VIA_HAS_RNG 1 /* cpu has RNG */ 976 977 /* VIA ACE crypto featureset: for via_feature_xcrypt */ 978 #define VIA_HAS_AES 1 /* cpu has AES */ 979 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 980 #define VIA_HAS_MM 4 /* cpu has RSA instructions */ 981 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 982 983 /* Centaur Extended Feature flags */ 984 #define VIA_CPUID_HAS_RNG 0x000004 985 #define VIA_CPUID_DO_RNG 0x000008 986 #define VIA_CPUID_HAS_ACE 0x000040 987 #define VIA_CPUID_DO_ACE 0x000080 988 #define VIA_CPUID_HAS_ACE2 0x000100 989 #define VIA_CPUID_DO_ACE2 0x000200 990 #define VIA_CPUID_HAS_PHE 0x000400 991 #define VIA_CPUID_DO_PHE 0x000800 992 #define VIA_CPUID_HAS_PMM 0x001000 993 #define VIA_CPUID_DO_PMM 0x002000 994 995 /* VIA ACE xcrypt-* instruction context control options */ 996 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 997 #define VIA_CRYPT_CWLO_ALG_M 0x00000070 998 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000 999 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 1000 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 1001 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 1002 #define VIA_CRYPT_CWLO_NORMAL 0x00000000 1003 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 1004 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 1005 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200 1006 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 1007 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 1008 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 1009 1010 #endif /* !_MACHINE_SPECIALREG_H_ */ 1011