| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| HD | HexagonRegisterInfo.cpp | 44 HexagonRegisterInfo::HexagonRegisterInfo(unsigned HwMode) in HexagonRegisterInfo() function in HexagonRegisterInfo
49 bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(unsigned R) const { in isEHReturnCalleeSaveReg()
55 HexagonRegisterInfo::getCallerSavedRegs(const MachineFunction *MF, in getCallerSavedRegs()
107 HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { in getCalleeSavedRegs()
129 const uint32_t *HexagonRegisterInfo::getCallPreservedMask( in getCallPreservedMask()
135 BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF) in getReservedRegs()
185 void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, in eliminateFrameIndex()
240 bool HexagonRegisterInfo::shouldCoalesce(MachineInstr *MI, in shouldCoalesce()
289 unsigned HexagonRegisterInfo::getRARegister() const { in getRARegister()
294 Register HexagonRegisterInfo::getFrameRegister(const MachineFunction in getFrameRegister()
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| HD | HexagonRegisterInfo.h | 29 class HexagonRegisterInfo : public HexagonGenRegisterInfo {
31 HexagonRegisterInfo(unsigned HwMode);
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| HD | HexagonBitTracker.h | 19 class HexagonRegisterInfo; variable
31 HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri,
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| HD | HexagonFrameLowering.h | 24 class HexagonRegisterInfo; variable
117 const HexagonRegisterInfo &HRI, bool &PrologueStubs) const;
119 const HexagonRegisterInfo &HRI) const;
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| HD | HexagonVLIWPacketizer.h | 20 class HexagonRegisterInfo; variable
67 const HexagonRegisterInfo *HRI;
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| HD | HexagonISelDAGToDAG.h | 27 class HexagonRegisterInfo; variable
33 const HexagonRegisterInfo *HRI;
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| HD | HexagonSubtarget.h | 88 HexagonRegisterInfo RegInfo;
104 const HexagonRegisterInfo *getRegisterInfo() const override { in getRegisterInfo()
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| HD | HexagonConstExtenders.cpp | 383 const HexagonRegisterInfo *HRI = nullptr;
444 PrintRegister(HCE::Register R, const HexagonRegisterInfo &I) in PrintRegister()
447 const HexagonRegisterInfo &HRI;
460 PrintExpr(const HCE::ExtExpr &E, const HexagonRegisterInfo &I) in PrintExpr()
463 const HexagonRegisterInfo &HRI;
478 PrintInit(const HCE::ExtenderInit &EI, const HexagonRegisterInfo &I) in PrintInit()
481 const HexagonRegisterInfo &HRI;
549 PrintIMap(const HCE::AssignmentMap &M, const HexagonRegisterInfo &I) in PrintIMap()
552 const HexagonRegisterInfo &HRI;
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| HD | HexagonBranchRelaxation.cpp | 69 const HexagonRegisterInfo *HRI;
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| HD | HexagonBitSimplify.cpp | 438 auto &HRI = static_cast<const HexagonRegisterInfo&>( in parseRegSequence()
902 auto &HRI = static_cast<const HexagonRegisterInfo&>( in getFinalVRegClass()
1053 const HexagonRegisterInfo &hri, MachineRegisterInfo &mri) in RedundantInstrElimination()
1069 const HexagonRegisterInfo &HRI;
1498 const HexagonRegisterInfo &hri, MachineRegisterInfo &mri) in CopyGeneration()
1508 const HexagonRegisterInfo &HRI;
1518 CopyPropagation(const HexagonRegisterInfo &hri, MachineRegisterInfo &mri) in CopyPropagation()
1528 const HexagonRegisterInfo &HRI;
1741 const HexagonInstrInfo &hii, const HexagonRegisterInfo &hri, in BitSimplification()
1785 const HexagonRegisterInfo &HRI;
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| HD | HexagonNewValueJump.cpp | 97 const HexagonRegisterInfo *QRI;
461 QRI = static_cast<const HexagonRegisterInfo *>( in runOnMachineFunction()
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| HD | HexagonVectorPrint.cpp | 55 const HexagonRegisterInfo *QRI = nullptr;
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| HD | HexagonPeephole.cpp | 83 const HexagonRegisterInfo *QRI;
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| HD | HexagonBitTracker.cpp | 40 HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri, in HexagonEvaluator()
95 const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI); in mask()
138 const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI); in composeWithSubRegIndex()
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| HD | HexagonGenMux.cpp | 89 const HexagonRegisterInfo *HRI = nullptr;
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| HD | HexagonRegisterInfo.td | 1 //===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===//
141 // as reserved in HexagonRegisterInfo.cpp.
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| HD | HexagonInstrInfo.cpp | 126 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) { in isDblRegForSubInst()
791 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in copyPhysReg()
987 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in expandPostRAPseudo()
1621 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in DefinesPredicate()
2092 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in isDependent()
3727 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in getDuplexCandidateGroup()
4099 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in getOperandLatency()
4212 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in getMemAccessSize()
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| HD | HexagonStoreWidening.cpp | 66 const HexagonRegisterInfo *TRI;
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| HD | HexagonGenPredicate.cpp | 108 const HexagonRegisterInfo *TRI = nullptr;
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| HD | HexagonFrameLowering.cpp | 283 const HexagonRegisterInfo &HRI) { in needsStackFrame()
1211 const CSIVect &CSI, const HexagonRegisterInfo &HRI, in insertCSRSpillsInBlock()
1279 const CSIVect &CSI, const HexagonRegisterInfo &HRI) const { in insertCSRRestoresInBlock()
1430 const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) { in needToReserveScavengingSpillSlots()
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| HD | Hexagon.td | 311 include "HexagonRegisterInfo.td"
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| HD | HexagonOptAddrMode.cpp | 84 const HexagonRegisterInfo *HRI = nullptr;
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| HD | HexagonISelLowering.cpp | 427 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerCall()
632 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerINLINEASM()
1021 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerRETURNADDR()
1047 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerFRAMEADDR()
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| HD | HexagonVLIWPacketizer.cpp | 116 const HexagonRegisterInfo *HRI = nullptr;
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| HD | HexagonSplitDouble.cpp | 84 const HexagonRegisterInfo *TRI = nullptr;
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