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Searched refs:GPR64RegClass (Results 1 – 23 of 23) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsOptionRecord.h48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
67 const MCRegisterClass *GPR64RegClass; variable
HDMipsMachineFunction.cpp42 return Mips::GPR64RegClass; in getGlobalBaseRegClass()
75 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
155 ? Mips::GPR64RegClass in createEhDataRegsFI()
HDMipsSERegisterInfo.cpp59 return &Mips::GPR64RegClass; in intRegClass()
223 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in eliminateFI()
HDMipsSEInstrInfo.cpp149 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg. in copyPhysReg()
150 if (Mips::GPR64RegClass.contains(SrcReg)) in copyPhysReg()
159 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg. in copyPhysReg()
256 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
334 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
614 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in loadImmediate()
HDMipsSEFrameLowering.cpp422 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitPrologue()
720 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitEpilogue()
896 Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
913 ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
HDMipsSubtarget.cpp229 CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass in getCriticalPathRCs()
HDMipsRegisterInfo.cpp54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
HDMipsSEISelLowering.cpp71 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); in MipsSETargetLowering()
3340 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitINSERT_DF_VIDX()
3526 : &Mips::GPR64RegClass); in emitST_F16_PSEUDO()
3532 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass); in emitST_F16_PSEUDO()
3578 : &Mips::GPR64RegClass); in emitLD_F16_PSEUDO()
3670 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitFPROUND_PSEUDO()
3774 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitFPEXTEND_PSEUDO()
HDMipsISelLowering.cpp4096 return std::make_pair(0U, &Mips::GPR64RegClass); in getRegForInlineAsmConstraint()
4120 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); in getRegForInlineAsmConstraint()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
HDBPFMIChecking.cpp107 const MCRegisterClass *GPR64RegClass = in hasLiveDefs() local
118 RegIsGPR64 = GPR64RegClass->contains(MO.getReg()); in hasLiveDefs()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64FastISel.cpp388 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass in materializeInt()
421 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()
484 ResultReg = createResultReg(&AArch64::GPR64RegClass); in materializeGV()
497 unsigned Result64 = createResultReg(&AArch64::GPR64RegClass); in materializeGV()
1336 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rr()
1379 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_ri()
1423 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rs()
1466 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rx()
1767 RC = &AArch64::GPR64RegClass; in emitLogicalOp_rs()
1869 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
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HDAArch64RegisterInfo.cpp260 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV. in getCrossCopyRegClass()
505 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in eliminateFrameIndex()
535 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in eliminateFrameIndex()
HDAArch64AdvSIMDScalarPass.cpp109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
110 return AArch64::GPR64RegClass.contains(Reg); in isGPR64()
HDAArch64CleanupLocalDynamicTLSPass.cpp122 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass); in setRegister()
HDAArch64InstrInfo.cpp626 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { in insertSelect()
627 RC = &AArch64::GPR64RegClass; in insertSelect()
1609 AArch64::GPR64RegClass.contains(DstReg)); in isGPRCopy()
2776 AArch64::GPR64RegClass.contains(SrcReg)) { in copyPhysReg()
2781 if (AArch64::GPR64RegClass.contains(DestReg) && in copyPhysReg()
2802 assert(AArch64::GPR64RegClass.contains(SrcReg) && "Invalid NZCV copy"); in copyPhysReg()
2811 assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy"); in copyPhysReg()
2880 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass); in storeRegToStackSlot()
3022 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass); in loadRegFromStackSlot()
3260 MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass); in foldMemoryOperandImpl()
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HDAArch64FrameLowering.cpp427 for (unsigned Reg : AArch64::GPR64RegClass) { in findScratchNonCalleeSaveRegister()
1973 if (AArch64::GPR64RegClass.contains(RPI.Reg1)) in computeCalleeSaveRegisterPairs()
1991 if (AArch64::GPR64RegClass.contains(NextReg) && in computeCalleeSaveRegisterPairs()
2379 if (AArch64::GPR64RegClass.contains(Reg) || in determineCalleeSaves()
2385 if (AArch64::GPR64RegClass.contains(Reg) && in determineCalleeSaves()
2399 if (AArch64::GPR64RegClass.contains(PairedReg) && in determineCalleeSaves()
2474 const TargetRegisterClass &RC = AArch64::GPR64RegClass; in determineCalleeSaves()
HDAArch64InstructionSelector.cpp341 : &AArch64::GPR64RegClass; in getRegClassForTypeOnBank()
373 : &AArch64::GPR64RegClass; in getMinClassForRegBank()
1189 Register ArgsAddrReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectVaStartDarwin()
1218 auto MovZ = MIB.buildInstr(AArch64::MOVZXi, {&AArch64::GPR64RegClass}, {}); in materializeLargeCMVal()
1229 : MRI.createVirtualRegister(&AArch64::GPR64RegClass); in materializeLargeCMVal()
1399 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI); in earlySelect()
1639 DefSize == 32 ? AArch64::GPR32RegClass : AArch64::GPR64RegClass; in select()
2078 SrcRC == &AArch64::GPR64RegClass) { in select()
2200 MIB.buildInstr(AArch64::SUBREG_TO_REG, {&AArch64::GPR64RegClass}, {}) in select()
2436 Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectBrJT()
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HDAArch64CollectLOH.cpp470 for (MCPhysReg Reg : AArch64::GPR64RegClass) in handleNormalInst()
HDAArch64FalkorHWPFFix.cpp751 for (unsigned ScratchReg : AArch64::GPR64RegClass) { in runOnLoop()
HDAArch64CallLowering.cpp405 unsigned X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass); in handleMustTailForwardedRegisters()
HDAArch64LoadStoreOptimizer.cpp1069 LdRt, AArch64::sub_32, &AArch64::GPR64RegClass)) in promoteLoadFromStore()
HDAArch64ISelLowering.cpp3406 RC = &AArch64::GPR64RegClass; in LowerFormalArguments()
3535 unsigned X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass); in LowerFormalArguments()
3619 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass); in saveVarArgRegisters()
4448 if (AArch64::GPR64RegClass.contains(*I)) in LowerReturn()
5874 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass); in LowerRETURNADDR()
13320 if (AArch64::GPR64RegClass.contains(*I)) in insertCopiesSplitCSR()
13321 RC = &AArch64::GPR64RegClass; in insertCopiesSplitCSR()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
HDMipsOptionRecord.cpp81 if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg)) in SetPhysRegUsed()