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Searched refs:GPR32RegClass (Results 1 – 25 of 27) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsFastISel.cpp329 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp()
345 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in fastMaterializeAlloca()
359 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeInt()
396 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass); in materializeFP()
402 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass); in materializeFP()
404 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass); in materializeFP()
415 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeGV()
437 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeExternalCallSym()
653 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
659 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
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HDMipsInstructionSelector.cpp122 return &Mips::GPR32RegClass; in getRegClassForTypeOnBank()
162 Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass); in materialize32BitImm()
338 Register JTIndex = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
346 Register DestAddress = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
354 Register Dest = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
366 Register DestTmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
499 Register GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
510 Register GPRRegHigh = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
511 Register GPRRegLow = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
590 Register LWGOTDef = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
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HDMipsMachineFunction.cpp44 return Mips::GPR32RegClass; in getGlobalBaseRegClass()
75 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
156 : Mips::GPR32RegClass; in createEhDataRegsFI()
168 const TargetRegisterClass &RC = Mips::GPR32RegClass; in createISRRegFI()
HDMipsOptionRecord.h47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
66 const MCRegisterClass *GPR32RegClass; variable
HDMipsSEFrameLowering.cpp317 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64()
385 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass; in expandExtractElementF64()
422 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitPrologue()
591 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass; in emitInterruptPrologueStub()
720 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitEpilogue()
754 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass; in emitInterruptEpilogueStub()
896 Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
913 ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
HDMipsSERegisterInfo.cpp56 return &Mips::GPR32RegClass; in intRegClass()
223 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in eliminateFI()
HDMipsSEInstrInfo.cpp90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
91 if (Mips::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
118 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg. in copyPhysReg()
254 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
332 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
614 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in loadImmediate()
HDMips16InstrInfo.cpp76 Mips::GPR32RegClass.contains(SrcReg)) in copyPhysReg()
78 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
HDMipsSubtarget.cpp230 : &Mips::GPR32RegClass); in getCriticalPathRCs()
HDMipsRegisterInfo.cpp54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
HDMipsSEISelLowering.cpp68 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); in MipsSETargetLowering()
3039 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in emitBPOSGE32()
3108 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in emitMSACBranchPseudo()
3340 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitINSERT_DF_VIDX()
3525 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass in emitST_F16_PSEUDO()
3527 const bool UsingMips32 = RC == &Mips::GPR32RegClass; in emitST_F16_PSEUDO()
3528 Register Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass); in emitST_F16_PSEUDO()
3577 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass in emitLD_F16_PSEUDO()
3580 const bool UsingMips32 = RC == &Mips::GPR32RegClass; in emitLD_F16_PSEUDO()
3589 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass); in emitLD_F16_PSEUDO()
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HDMipsAsmPrinter.cpp338 unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8; in printSavedRegsBitmask()
357 } else if (Mips::GPR32RegClass.contains(Reg)) in printSavedRegsBitmask()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
HDARCInstrInfo.cpp285 assert(ARC::GPR32RegClass.contains(SrcReg) && in copyPhysReg()
287 assert(ARC::GPR32RegClass.contains(DestReg) && in copyPhysReg()
311 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
338 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in loadRegFromStackSlot()
HDARCRegisterInfo.cpp60 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); in ReplaceFrameIndex()
66 BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); in ReplaceFrameIndex()
210 assert(ARC::GPR32RegClass.contains(Reg) && "Unexpected register operand"); in eliminateFrameIndex()
HDARCExpandPseudos.cpp62 unsigned AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in ExpandStore()
HDARCISelLowering.cpp76 addRegisterClass(MVT::i32, &ARC::GPR32RegClass); in ARCTargetLowering()
493 unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass); in LowerCallArguments()
538 unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass); in LowerCallArguments()
HDARCFrameLowering.cpp442 const TargetRegisterClass *RC = &ARC::GPR32RegClass; in processFunctionBeforeFrameFinalized()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
HDBPFInstrInfo.cpp38 else if (BPF::GPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
138 else if (RC == &BPF::GPR32RegClass) in storeRegToStackSlot()
158 else if (RC == &BPF::GPR32RegClass) in loadRegFromStackSlot()
HDBPFMISimplifyPatchable.cpp159 if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) { in processCandidate()
HDBPFISelLowering.cpp64 addRegisterClass(MVT::i32, &BPF::GPR32RegClass); in BPFTargetLowering()
240 SimpleTy == MVT::i64 ? &BPF::GPRRegClass : &BPF::GPR32RegClass); in LowerFormalArguments()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64FastISel.cpp389 : &AArch64::GPR32RegClass; in materializeInt()
421 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()
481 ResultReg = createResultReg(&AArch64::GPR32RegClass); in materializeGV()
1336 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rr()
1379 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_ri()
1423 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rs()
1466 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rx()
1763 RC = &AArch64::GPR32RegClass; in emitLogicalOp_rs()
1869 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
1874 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
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HDAArch64InstructionSelector.cpp338 : &AArch64::GPR32RegClass; in getRegClassForTypeOnBank()
370 : &AArch64::GPR32RegClass; in getMinClassForRegBank()
1402 RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI); in earlySelect()
1639 DefSize == 32 ? AArch64::GPR32RegClass : AArch64::GPR64RegClass; in select()
1729 AArch64::GPR32RegClass, MRI); in select()
1764 AArch64::GPR32RegClass, MRI); in select()
1901 Register LdReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass); in select()
2077 } else if (DstRC == &AArch64::GPR32RegClass && in select()
2193 if (!RBI.constrainGenericRegister(SrcReg, AArch64::GPR32RegClass, MRI)) { in select()
2337 Def1Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass); in select()
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HDAArch64InstrInfo.cpp630 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) { in insertSelect()
631 RC = &AArch64::GPR32RegClass; in insertSelect()
1608 return (AArch64::GPR32RegClass.contains(DstReg) || in isGPRCopy()
2789 AArch64::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
2794 if (AArch64::GPR32RegClass.contains(DestReg) && in copyPhysReg()
2870 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass); in storeRegToStackSlot()
3012 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass); in loadRegFromStackSlot()
3345 if (AArch64::GPR32RegClass.contains(SrcReg)) { in foldMemoryOperandImpl()
3388 FillRC = &AArch64::GPR32RegClass; in foldMemoryOperandImpl()
4384 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
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HDAArch64CollectLOH.cpp468 for (MCPhysReg Reg : AArch64::GPR32RegClass) in handleNormalInst()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
HDMipsOptionRecord.cpp81 if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg)) in SetPhysRegUsed()

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