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Searched refs:FSIN (Results 1 – 25 of 32) sorted by relevance

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/freebsd-11-stable/contrib/one-true-awk/
HDawk.h123 #define FSIN 9 macro
HDlex.c79 { "sin", FSIN, BLTIN },
HDrun.c1504 case FSIN: in bltin()
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/
HDConstrainedOps.def80 FUNCTION(sin, 1, 1, experimental_constrained_sin, FSIN)
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDISDOpcodes.h640 FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW, enumerator
HDBasicTTIImpl.h1223 ISDs.push_back(ISD::FSIN);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
HDSelectionDAGDumper.cpp196 case ISD::FSIN: return "fsin"; in getOperationName()
HDLegalizeFloatTypes.cpp117 case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break; in SoftenFloatResult()
1174 case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break; in ExpandFloatResult()
2120 case ISD::FSIN: in PromoteFloatResult()
HDLegalizeDAG.cpp2259 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN in useSinCos()
2260 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3192 case ISD::FSIN: in ExpandNode()
3960 case ISD::FSIN: in ConvertNodeToLibcall()
4509 case ISD::FSIN: in PromoteNode()
HDLegalizeVectorOps.cpp420 case ISD::FSIN: in LegalizeOp()
HDLegalizeVectorTypes.cpp96 case ISD::FSIN: in ScalarizeVectorResult()
890 case ISD::FSIN: in SplitVectorResult()
2816 case ISD::FSIN: in WidenVectorResult()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDR600ISelLowering.cpp145 setOperationAction(ISD::FSIN, MVT::f32, Custom); in R600TargetLowering()
488 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
775 case ISD::FSIN: in LowerTrig()
HDAMDGPUISelLowering.cpp424 setOperationAction(ISD::FSIN, VT, Expand); in AMDGPUTargetLowering()
522 case ISD::FSIN: in fnegFoldsIntoOp()
3809 case ISD::FSIN: in performFNegCombine()
HDSIISelLowering.cpp441 setOperationAction(ISD::FSIN, MVT::f32, Custom); in SITargetLowering()
503 setOperationAction(ISD::FSIN, MVT::f16, Promote); in SITargetLowering()
4048 case ISD::FSIN: in LowerOperation()
7993 case ISD::FSIN: in LowerTrig()
8607 case ISD::FSIN: in fp16SrcZerosHighBits()
8801 case ISD::FSIN: in isCanonicalized()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86ScheduleAtom.td891 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
HDX86InstrFPStack.td746 def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp1616 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1621 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1626 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp269 setOperationAction(ISD::FSIN, MVT::f128, Expand); in AArch64TargetLowering()
386 setOperationAction(ISD::FSIN, MVT::f32, Expand); in AArch64TargetLowering()
387 setOperationAction(ISD::FSIN, MVT::f64, Expand); in AArch64TargetLowering()
411 setOperationAction(ISD::FSIN, MVT::f16, Promote); in AArch64TargetLowering()
412 setOperationAction(ISD::FSIN, MVT::v4f16, Expand); in AArch64TargetLowering()
413 setOperationAction(ISD::FSIN, MVT::v8f16, Expand); in AArch64TargetLowering()
720 setOperationAction(ISD::FSIN, MVT::v1f64, Expand); in AArch64TargetLowering()
879 setOperationAction(ISD::FSIN, VT, Expand); in addTypeForNEON()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
HDWebAssemblyISelLowering.cpp94 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp1437 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1482 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMISelLowering.cpp349 setOperationAction(ISD::FSIN, VT, Expand); in addMVEVectorTypes()
798 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); in ARMTargetLowering()
819 setOperationAction(ISD::FSIN, MVT::v4f32, Expand); in ARMTargetLowering()
835 setOperationAction(ISD::FSIN, MVT::v2f32, Expand); in ARMTargetLowering()
964 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
1324 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
1325 setOperationAction(ISD::FSIN, MVT::f32, Expand); in ARMTargetLowering()
1408 setOperationAction(ISD::FSIN, MVT::f16, Promote); in ARMTargetLowering()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsISelLowering.cpp434 setOperationAction(ISD::FSIN, MVT::f32, Expand); in MipsTargetLowering()
435 setOperationAction(ISD::FSIN, MVT::f64, Expand); in MipsTargetLowering()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp290 setOperationAction(ISD::FSIN , MVT::f64, Expand); in PPCTargetLowering()
295 setOperationAction(ISD::FSIN , MVT::f32, Expand); in PPCTargetLowering()
666 setOperationAction(ISD::FSIN, VT, Expand); in PPCTargetLowering()
960 setOperationAction(ISD::FSIN , MVT::f128, Expand); in PPCTargetLowering()
1022 setOperationAction(ISD::FSIN , MVT::v4f64, Expand); in PPCTargetLowering()
1067 setOperationAction(ISD::FSIN , MVT::v4f32, Expand); in PPCTargetLowering()
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Target/
HDTargetSelectionDAG.td457 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
HDRISCVISelLowering.cpp164 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP, in RISCVTargetLowering()

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