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Searched refs:FP_ROUND (Results 1 – 25 of 25) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/
HDConstrainedOps.def48 INSTRUCTION(FPTrunc, 1, 1, experimental_constrained_fptrunc, FP_ROUND)
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDISDOpcodes.h599 FP_ROUND, enumerator
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeFloatTypes.cpp104 case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break; in SoftenFloatResult()
779 case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break; in SoftenFloatOperand()
824 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16 || in SoftenFloatOp_FP_ROUND()
988 Val = BitConvertToInteger(DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(), in SoftenFloatOp_STORE()
1661 case ISD::FP_ROUND: Res = ExpandFloatOp_FP_ROUND(N); break; in ExpandFloatOperand()
1761 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ExpandFloatOp_FP_ROUND()
2142 case ISD::FP_ROUND: R = PromoteFloatRes_FP_ROUND(N); break; in PromoteFloatResult()
2376 DAG.getNode(ISD::FP_ROUND, DL, VT, NV, DAG.getIntPtrConstant(0, DL))); in PromoteFloatRes_XINT_TO_FP()
HDLegalizeVectorTypes.cpp54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
305 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ScalarizeVecRes_FP_ROUND()
601 case ISD::FP_ROUND: in ScalarizeVectorOperand()
765 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ScalarizeVecOp_FP_ROUND()
885 case ISD::FP_ROUND: in SplitVectorResult()
1710 if (N->getOpcode() == ISD::FP_ROUND) { in SplitVecRes_UnaryOp()
1934 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; in SplitVectorOperand()
2599 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec, in SplitVecOp_TruncateHelper()
2651 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1)); in SplitVecOp_FP_ROUND()
2652 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1)); in SplitVecOp_FP_ROUND()
[all …]
HDLegalizeVectorOps.cpp435 case ISD::FP_ROUND: in LegalizeOp()
573 case ISD::FP_ROUND: in Promote()
612 Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res, DAG.getIntPtrConstant(0, dl)); in Promote()
HDLegalizeDAG.cpp2895 case ISD::FP_ROUND: in ExpandNode()
3231 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op, in ExpandNode()
4389 TruncOp = ISD::FP_ROUND; in PromoteNode()
4398 if (TruncOp != ISD::FP_ROUND) in PromoteNode()
4458 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4481 DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4497 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4519 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
HDSelectionDAGDumper.cpp327 case ISD::FP_ROUND: return "fp_round"; in getOperationName()
HDDAGCombiner.cpp1590 case ISD::FP_ROUND: return visitFP_ROUND(N); in visit()
9435 CastOpcode == ISD::FP_ROUND) && in matchVSelectOpSizesWithSetCC()
9461 if (CastOpcode == ISD::FP_ROUND) { in matchVSelectOpSizesWithSetCC()
12793 } else if (N1.getOpcode() == ISD::FP_ROUND && in visitFDIV()
12797 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N1), VT, RV, N1.getOperand(1)); in visitFDIV()
12875 N1.getOpcode() == ISD::FP_ROUND)) { in CanCombineFCOPYSIGN_EXTEND_ROUND()
13232 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1); in visitFP_ROUND()
13239 if (N0.getOpcode() == ISD::FP_ROUND) { in visitFP_ROUND()
13260 return DAG.getNode(ISD::FP_ROUND, DL, VT, N0.getOperand(0), in visitFP_ROUND()
13267 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT, in visitFP_ROUND()
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HDSelectionDAG.cpp1125 : getNode(ISD::FP_ROUND, DL, VT, Op, getIntPtrConstant(0, DL)); in getFPExtendOrRound()
4127 case ISD::FP_ROUND: { in isKnownNeverNaN()
4567 case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node"); in getNode()
5099 if (N1CFP && Opcode == ISD::FP_ROUND) { in foldConstantFPMath()
5254 case ISD::FP_ROUND: in getNode()
HDTargetLowering.cpp5600 case ISD::FP_ROUND: in isNegatibleForFree()
5722 case ISD::FP_ROUND: in getNegatedExpression()
5723 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(), in getNegatedExpression()
HDSelectionDAGBuilder.cpp325 ISD::FP_ROUND, DL, ValueVT, Val, in getCopyFromParts()
3448 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N, in visitFPTrunc()
6286 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16, in visitIntrinsicCall()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMTargetTransformInfo.cpp161 { ISD::FP_ROUND, MVT::v2f64, 2 }, in getCastInstrCost()
166 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND || in getCastInstrCost()
HDARMISelLowering.cpp873 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand); in ARMTargetLowering()
983 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in ARMTargetLowering()
995 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom); in ARMTargetLowering()
9379 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG); in LowerOperation()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp1717 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in SparcTargetLowering()
1745 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in SparcTargetLowering()
1746 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in SparcTargetLowering()
3051 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this); in LowerOperation()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.cpp2529 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
2569 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3830 case ISD::FP_ROUND: { in performFNegCombine()
3835 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3844 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
HDR600ISelLowering.cpp277 setTargetDAGCombine(ISD::FP_ROUND); in R600TargetLowering()
1849 case ISD::FP_ROUND: { in PerformDAGCombine()
HDSIISelLowering.cpp226 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand); in SITargetLowering()
501 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom); in SITargetLowering()
4074 case ISD::FP_ROUND: in LowerOperation()
7651 SDValue BestQuot = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag); in LowerFDIV16()
8600 case ISD::FP_ROUND: in fp16SrcZerosHighBits()
8771 case ISD::FP_ROUND: in isCanonicalized()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86ISelDAGToDAG.cpp819 case ISD::FP_ROUND: in PreprocessISelDAG()
833 case ISD::FP_ROUND: NewOpc = X86ISD::VFPROUND; break; in PreprocessISelDAG()
1034 case ISD::FP_ROUND: in PreprocessISelDAG()
1065 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
HDX86TargetTransformInfo.cpp1338 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, in getCastInstrCost()
1436 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, in getCastInstrCost()
1517 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, in getCastInstrCost()
HDX86ISelLowering.cpp718 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in X86TargetLowering()
722 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in X86TargetLowering()
726 setOperationAction(ISD::FP_ROUND, MVT::f80, Custom); in X86TargetLowering()
998 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom); in X86TargetLowering()
3061 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, in LowerCallResult()
19416 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, in LowerUINT_TO_FP()
20490 Sign = DAG.getNode(ISD::FP_ROUND, dl, VT, Sign, DAG.getIntPtrConstant(1, dl)); in LowerFCOPYSIGN()
28585 case ISD::FP_ROUND: in LowerOperation()
29259 case ISD::FP_ROUND: { in ReplaceNodeResults()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp954 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in PPCTargetLowering()
955 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal); in PPCTargetLowering()
1017 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal); in PPCTargetLowering()
8089 Value = DAG.getNode(ISD::FP_ROUND, dl, in LowerINT_TO_FP()
8239 FP = DAG.getNode(ISD::FP_ROUND, dl, in LowerINT_TO_FP()
8312 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
8572 (V->getOperand(i).getOpcode() == ISD::FP_ROUND && in haveEfficientBuildVectorPattern()
13027 SDValue Trunc = DAG.getNode(ISD::FP_ROUND, dl, in combineElementTruncationToVectorTruncation()
13072 if (FirstInput.getOpcode() == ISD::FP_ROUND && in combineBVOfConsecutiveLoads()
13084 if (IsRoundOfExtLoad && N->getOperand(i).getOpcode() != ISD::FP_ROUND) in combineBVOfConsecutiveLoads()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp308 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in AArch64TargetLowering()
309 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in AArch64TargetLowering()
735 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand); in AArch64TargetLowering()
2636 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl)); in LowerVectorINT_TO_FP()
2664 ISD::FP_ROUND, dl, MVT::f16, in LowerINT_TO_FP()
3204 case ISD::FP_ROUND: in LowerOperation()
5093 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0, DL)); in LowerFCOPYSIGN()
5781 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0), in LowerVAARG()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDTargetLoweringBase.cpp1627 case FPTrunc: return ISD::FP_ROUND; in InstructionOpcodeToISD()
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Target/
HDTargetSelectionDAG.td474 def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
HDSystemZISelLowering.cpp639 setTargetDAGCombine(ISD::FP_ROUND); in SystemZTargetLowering()
6391 case ISD::FP_ROUND: return combineFP_ROUND(N, DCI); in PerformDAGCombine()