Home
last modified time | relevance | path

Searched refs:FMA (Results 1 – 25 of 61) sorted by relevance

123

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86InstrFMA.td1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//
9 // This file describes FMA (Fused Multiply-Add) instructions.
17 // For all FMA opcodes declared in fma3p_rm_* and fma3s_rm_* multiclasses
23 // FMA*213*:
27 // FMA*132*:
31 // FMA*231*:
168 // All source register operands of FMA opcodes defined in fma3s_rm multiclass
170 // adjustment, for example, commuting the operands 1 and 2 in FMA*132 form
171 // would require an opcode change to FMA*231:
172 // FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2;
[all …]
HDX86IntrinsicsInfo.h935 X86_INTRINSIC_DATA(avx512_vfmadd_f32, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
936 X86_INTRINSIC_DATA(avx512_vfmadd_f64, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
937 X86_INTRINSIC_DATA(avx512_vfmadd_pd_512, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
938 X86_INTRINSIC_DATA(avx512_vfmadd_ps_512, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
HDX86ScheduleSLM.td481 // AVX/FMA is not supported on that architecture, but we should define the basic
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDAMDGPUFeatures.td16 "FMA",
18 "Enable single precision FMA (not as fast as mul+add, but fused)"
HDAMDGPUSubtarget.h320 bool FMA; variable
550 return FMA; in hasFMA()
1224 bool FMA; variable
1309 bool hasFMA() const { return FMA; } in hasFMA()
HDSIISelLowering.cpp521 setOperationAction(ISD::FMA, MVT::f16, Legal); in SITargetLowering()
627 setOperationAction(ISD::FMA, MVT::v2f16, Legal); in SITargetLowering()
654 setOperationAction(ISD::FMA, MVT::v4f16, Custom); in SITargetLowering()
726 setTargetDAGCombine(ISD::FMA); in SITargetLowering()
783 (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) && in isFPExtFoldable()
4087 case ISD::FMA: in LowerOperation()
7627 case ISD::FMA: in getFPTernOp()
7760 SDValue Fma0 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, in LowerFDIV32()
7763 SDValue Fma1 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, Fma0, ApproxRcp, in LowerFDIV32()
7769 SDValue Fma2 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Mul, in LowerFDIV32()
[all …]
HDAMDGPUInstrInfo.td239 // Special case divide FMA with scale and flags (src0 = Quotient,
HDAMDGPUSubtarget.cpp537 FMA(false), in R600Subtarget()
HDAMDGPUInstructions.td113 def FMA : Predicate<"Subtarget->hasFMA()">;
HDR600Instructions.td1013 inst, "FMA",
1017 let OtherPredicates = [FMA];
/freebsd-11-stable/sys/cddl/dev/dtrace/x86/
HDdis_tables.c244 FMA, /* FMA instructions, all VEX_RMrX */ enumerator
1550 /* [94] */ INVALID, INVALID, TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16),
1551 /* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vf…
1552 /* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ(…
1555 /* [A4] */ INVALID, INVALID, TNSZ("vfmaddsub213p",FMA,16),TNSZ("vfmsubadd213p",FMA,16),
1556 /* [A8] */ TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vf…
1557 /* [AC] */ TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ(…
1560 /* [B4] */ INVALID, INVALID, TNSZ("vfmaddsub231p",FMA,16),TNSZ("vfmsubadd231p",FMA,16),
1561 /* [B8] */ TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vf…
1562 /* [BC] */ TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ(…
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/
HDConstrainedOps.def63 FUNCTION(fma, 3, 1, experimental_constrained_fma, FMA)
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDISDOpcodes.h356 FMA, enumerator
HDBasicTTIImpl.h1284 ISDs.push_back(ISD::FMA);
1287 ISDs.push_back(ISD::FMA);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/IR/
HDAutoUpgrade.cpp3141 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), IID); in UpgradeIntrinsicCall() local
3142 Rep = Builder.CreateCall(FMA, Ops); in UpgradeIntrinsicCall()
3144 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), in UpgradeIntrinsicCall() local
3147 Rep = Builder.CreateCall(FMA, { A, B, C }); in UpgradeIntrinsicCall()
3201 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), in UpgradeIntrinsicCall() local
3204 Rep = Builder.CreateCall(FMA, { A, B, C }); in UpgradeIntrinsicCall()
3220 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), Intrinsic::fma, in UpgradeIntrinsicCall() local
3222 Value *Odd = Builder.CreateCall(FMA, Ops); in UpgradeIntrinsicCall()
3224 Value *Even = Builder.CreateCall(FMA, Ops); in UpgradeIntrinsicCall()
3267 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), Intrinsic::fma, in UpgradeIntrinsicCall() local
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDInterleavedLoadCombinePass.cpp1184 auto FMA = MSSA.getMemoryAccess(First); in combine() local
1187 if (!MSSA.dominates(MADef, FMA)) in combine()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
HDPPCScheduleP7.td68 // FMA from the VSUs can forward results in 6 cycles. VS1 XS and vector FP
HDPPC.td322 // FMA instruction forms with their corresponding factor-killing forms.
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
HDSelectionDAGDumper.cpp256 case ISD::FMA: return "fma"; in getOperationName()
HDDAGCombiner.cpp1580 case ISD::FMA: return visitFMA(N); in visit()
11534 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT)); in visitFADDForFMACombine()
11553 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFADDForFMACombine()
11751 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT)); in visitFSUBForFMACombine()
11771 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFSUBForFMACombine()
12060 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT)); in visitFMULForFMADistributiveCombine()
12072 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFMULForFMADistributiveCombine()
12091 if (SDValue FMA = FuseFADD(N0, N1, Flags)) in visitFMULForFMADistributiveCombine() local
12092 return FMA; in visitFMULForFMADistributiveCombine()
12093 if (SDValue FMA = FuseFADD(N1, N0, Flags)) in visitFMULForFMADistributiveCombine() local
[all …]
HDLegalizeFloatTypes.cpp95 case ISD::FMA: R = SoftenFloatRes_FMA(N); break; in SoftenFloatResult()
1157 case ISD::FMA: ExpandFloatRes_FMA(N, Lo, Hi); break; in ExpandFloatResult()
2137 case ISD::FMA: // FMA is same as FMAD in PromoteFloatResult()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
HDNVPTXInstrInfo.td257 // In this case, we use the ".rn" variant when FMA is disabled, as this behaves
992 // FMA
995 multiclass FMA<string OpcStr, RegisterClass RC, Operand ImmCls, Predicate Pred> {
1028 defm FMA32_ftz : FMA<"fma.rn.ftz.f32", Float32Regs, f32imm, doF32FTZ>;
1029 defm FMA32 : FMA<"fma.rn.f32", Float32Regs, f32imm, true>;
1030 defm FMA64 : FMA<"fma.rn.f64", Float64Regs, f64imm, true>;
/freebsd-11-stable/contrib/llvm-project/clang/include/clang/Basic/
HDarm_neon.td687 // MUL, MLA, MLS, FMA, FMS definitions with scalar argument
1598 // FMA lane
1602 // FMA lane with scalar argument
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Support/
HDTargetOpcodes.def454 /// Generic FMA multiplication. Behaves like llvm fma intrinsic
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp1481 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV, in HexagonTargetLowering()
1583 setOperationAction(ISD::FMA, MVT::f64, Expand); in HexagonTargetLowering()
1910 return isOperationLegalOrCustom(ISD::FMA, VT); in isFMAFasterThanFMulAndFAdd()

123