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Searched refs:DefaultMode (Results 1 – 12 of 12) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
HDInfoByHwMode.h36 DefaultMode = CodeGenHwModes::DefaultMode, enumerator
51 if (M != DefaultMode) in union_modes()
56 V.push_back(DefaultMode); in union_modes()
84 bool hasDefault() const { return hasMode(DefaultMode); } in hasDefault()
88 assert(hasMode(DefaultMode)); in get()
89 Map.insert({Mode, Map.at(DefaultMode)}); in get()
95 if (Mode != DefaultMode && F == Map.end()) in get()
96 F = Map.find(DefaultMode); in get()
103 return Map.size() == 1 && Map.begin()->first == DefaultMode; in isSimple()
114 Map.insert(std::make_pair(DefaultMode, I)); in makeSimple()
[all …]
HDRegisterBankEmitter.cpp87 else if (RCWithLargestRegsSize->RSI.get(DefaultMode).SpillSize < in addRegisterClass()
88 RC->RSI.get(DefaultMode).SpillSize) in addRegisterClass()
246 unsigned Size = RC.RSI.get(DefaultMode).SpillSize; in emitBaseClassImplementation()
HDCodeGenHwModes.h42 enum : unsigned { DefaultMode = 0 }; enumerator
HDInfoByHwMode.cpp27 if (Mode == DefaultMode) in getModeName()
69 auto D = Map.find(DefaultMode); in getOrCreateTypeForMode()
HDCodeGenHwModes.cpp81 return DefaultMode; in getHwModeId()
HDCodeGenDAGPatterns.cpp121 if (DefaultMode == M) { in insert()
143 if (M == DefaultMode || hasMode(M)) in constrain()
145 Map.insert({M, Map.at(DefaultMode)}); in constrain()
756 const TypeSetByHwMode::SetType &LegalTypes = Legal.get(DefaultMode); in expandOverloads()
819 TypeSetByHwMode::SetType &LegalTypes = LegalCache.getOrCreate(DefaultMode); in getLegalTypes()
1710 if (S.get(DefaultMode).empty()) in setDefaultMode()
4314 if (M == DefaultMode) in ExpandHwModeBasedTypes()
4328 if (M == DefaultMode) in ExpandHwModeBasedTypes()
4333 bool HasDefault = Modes.count(DefaultMode); in ExpandHwModeBasedTypes()
4335 AppendPattern(P, DefaultMode); in ExpandHwModeBasedTypes()
HDCodeGenDAGPatterns.h228 return Map.size() == 1 && Map.begin()->first == DefaultMode; in isDefaultOnly()
HDCodeGenRegisters.cpp802 RSI.Map.insert({DefaultMode, RI}); in CodeGenRegisterClass()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonRegisterInfo.td285 def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
287 def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
289 def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
291 def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
294 def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
296 def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
298 def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
301 def VecQ8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
303 def VecQ16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
305 def VecQ32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
HDRISCVRegisterInfo.td86 def XLenVT : ValueTypeByHwMode<[RV32, RV64, DefaultMode],
100 [RV32, RV64, DefaultMode],
106 [RV32, RV64, DefaultMode],
121 [RV32, RV64, DefaultMode],
134 [RV32, RV64, DefaultMode],
143 [RV32, RV64, DefaultMode],
156 [RV32, RV64, DefaultMode],
162 [RV32, RV64, DefaultMode],
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDSIModeRegister.cpp130 unsigned DefaultMode = FP_ROUND_ROUND_TO_NEAREST; member in __anon2d3c15700111::SIModeRegister
132 Status(FP_ROUND_MODE_DP(0x3), FP_ROUND_MODE_DP(DefaultMode));
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Target/
HDTarget.td36 def DefaultMode : HwMode<"">;