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Searched refs:DRC (Results 1 – 11 of 11) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsCondMov.td18 class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
20 InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
26 class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
28 InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
55 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
59 def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
60 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
61 def : MipsPat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
62 (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
63 def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
[all …]
HDMipsInstrFPU.td213 class LWXC1_FT<string opstr, RegisterOperand DRC,
215 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
217 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
222 class SWXC1_FT<string opstr, RegisterOperand DRC,
224 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
226 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
HDMipsInstrInfo.td1804 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
1805 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
1806 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]> {
1823 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
1824 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1825 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]> {
/freebsd-11-stable/sys/dev/sound/macio/
HDtumbler.c183 u_char DRC[2]; member
229 sizeof tumbler_initdata.DRC, /* 0x02 */
359 tumbler_write(sc, TUMBLER_DRC, tumbler_initdata.DRC); in tumbler_init()
HDsnapper.c194 u_char DRC[6]; member
256 sizeof snapper_initdata.DRC, /* 0x02 */
408 snapper_write(sc, SNAPPER_DRC, snapper_initdata.DRC); in snapper_init()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonEarlyIfConv.cpp203 const TargetRegisterClass *DRC, unsigned PredR, unsigned TR,
778 MachineBasicBlock::iterator At, const TargetRegisterClass *DRC, in buildMux() argument
781 switch (DRC->getID()) { in buildMux()
802 Register MuxR = MRI->createVirtualRegister(DRC); in buildMux()
HDHexagonBitSimplify.cpp932 auto *DRC = getFinalVRegClass(RD, MRI); in isTransparentCopy() local
933 if (!DRC) in isTransparentCopy()
936 return DRC == getFinalVRegClass(RS, MRI); in isTransparentCopy()
1474 const BitTracker::RegisterCell &DRC = BT.lookup(DR); in processBlock() local
1475 if (HBS::getConst(DRC, 0, DRC.width(), U)) { in processBlock()
1482 BT.put(ImmReg, DRC); in processBlock()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
HDAVRInstrInfo.td1263 class AtomicLoad<PatFrag Op, RegisterClass DRC,
1265 Pseudo<(outs DRC:$rd), (ins PTRRC:$rr), "atomic_op",
1266 [(set DRC:$rd, (Op i16:$rr))]>;
1268 class AtomicStore<PatFrag Op, RegisterClass DRC,
1270 Pseudo<(outs), (ins PTRRC:$rd, DRC:$rr), "atomic_op",
1271 [(Op i16:$rd, DRC:$rr)]>;
1273 class AtomicLoadOp<PatFrag Op, RegisterClass DRC,
1275 Pseudo<(outs DRC:$rd), (ins PTRRC:$rr, DRC:$operand),
1277 [(set DRC:$rd, (Op i16:$rr, DRC:$operand))]>;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDMachineVerifier.cpp1687 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
1689 if (!DRC->contains(Reg)) { in visitMachineOperand()
1692 << TRI->getRegClassName(DRC) << " register.\n"; in visitMachineOperand()
1787 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
1796 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
1797 if (!DRC) { in visitMachineOperand()
1802 if (!RC->hasSuperClassEq(DRC)) { in visitMachineOperand()
1804 errs() << "Expected a " << TRI->getRegClassName(DRC) in visitMachineOperand()
HDMachineSink.cpp232 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
233 if (SRC != DRC) in INITIALIZE_PASS_DEPENDENCY()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDSIInstrInfo.cpp3933 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass); in isLegalRegOperand() local
3940 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg()); in isLegalRegOperand()
3941 if (!DRC) in isLegalRegOperand()
3944 return RC->hasSuperClassEq(DRC); in isLegalRegOperand()