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Searched refs:CSR_WRITE_4 (Results 1 – 25 of 84) sorted by relevance

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/freebsd-11-stable/sys/dev/et/
HDif_et.c314 CSR_WRITE_4(sc, ET_PM, pmcfg); in et_attach()
426 CSR_WRITE_4(sc, ET_MII_CMD, 0); in et_miibus_readreg()
430 CSR_WRITE_4(sc, ET_MII_ADDR, val); in et_miibus_readreg()
433 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); in et_miibus_readreg()
457 CSR_WRITE_4(sc, ET_MII_CMD, 0); in et_miibus_readreg()
470 CSR_WRITE_4(sc, ET_MII_CMD, 0); in et_miibus_writereg()
474 CSR_WRITE_4(sc, ET_MII_ADDR, val); in et_miibus_writereg()
477 CSR_WRITE_4(sc, ET_MII_CTRL, in et_miibus_writereg()
497 CSR_WRITE_4(sc, ET_MII_CMD, 0); in et_miibus_writereg()
579 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); in et_miibus_statchg()
[all …]
/freebsd-11-stable/sys/dev/lge/
HDif_lge.c197 CSR_WRITE_4(sc, reg, \
201 CSR_WRITE_4(sc, reg, \
205 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
208 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
222 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
288 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
312 CSR_WRITE_4(sc, LGE_GMIICTL,
380 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
383 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
384 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
[all …]
/freebsd-11-stable/sys/dev/sis/
HDif_sis.c118 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val) macro
195 CSR_WRITE_4(sc, reg, \
199 CSR_WRITE_4(sc, reg, \
203 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
206 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
253 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); in sis_eeprom_idle()
418 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); in sis_read_mac()
419 CSR_WRITE_4(sc, SIS_CSR, 0); in sis_read_mac()
421 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); in sis_read_mac()
423 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); in sis_read_mac()
[all …]
/freebsd-11-stable/sys/dev/alc/
HDif_alc.c294 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in alc_mii_readreg_813x()
321 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in alc_mii_readreg_816x()
358 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in alc_mii_writereg_813x()
384 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in alc_mii_writereg_816x()
442 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); in alc_miibus_statchg()
474 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | in alc_miiext_readreg()
480 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in alc_miiext_readreg()
504 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | in alc_miiext_writereg()
510 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in alc_miiext_writereg()
711 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); in alc_get_macaddr_813x()
[all …]
/freebsd-11-stable/sys/dev/wb/
HDif_wb.c236 CSR_WRITE_4(sc, reg, \
240 CSR_WRITE_4(sc, reg, \
244 CSR_WRITE_4(sc, WB_SIO, \
248 CSR_WRITE_4(sc, WB_SIO, \
293 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
300 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
315 CSR_WRITE_4(sc, WB_SIO, 0);
372 CSR_WRITE_4(sc, WB_SIO, val); in wb_mii_bitbang_write()
429 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
430 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
[all …]
/freebsd-11-stable/sys/arm/amlogic/aml8726/
HDaml8726_rtc.c125 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val)) macro
136 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) & in aml8726_rtc_start_transfer()
152 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) | in aml8726_rtc_start_transfer()
164 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) | in aml8726_rtc_sclk_pulse()
171 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) & in aml8726_rtc_sclk_pulse()
182 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) | in aml8726_rtc_send_bit()
185 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) & in aml8726_rtc_send_bit()
200 CSR_WRITE_4(sc, AML_RTC_0_REG, in aml8726_rtc_send_addr()
280 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) & in aml8726_rtc_initialize()
301 CSR_WRITE_4(sc, AML_RTC_4_REG, ((sc->init.xo >> 8) & 0xff)); in aml8726_rtc_initialize()
[all …]
HDaml8726_usb_phy-m3.c103 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val)) macro
258 CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); in aml8726_usb_phy_attach()
267 CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); in aml8726_usb_phy_attach()
274 CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); in aml8726_usb_phy_attach()
281 CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); in aml8726_usb_phy_attach()
288 CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); in aml8726_usb_phy_attach()
295 CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); in aml8726_usb_phy_attach()
302 CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); in aml8726_usb_phy_attach()
309 CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); in aml8726_usb_phy_attach()
320 CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); in aml8726_usb_phy_attach()
[all …]
HDaml8726_sdxc-m8.c152 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val)) macro
206 CSR_WRITE_4(sc, AML_SDXC_SOFT_RESET_REG, AML_SDXC_SOFT_RESET); in aml8726_sdxc_soft_reset()
238 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar); in aml8726_sdxc_engage_dma()
245 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar); in aml8726_sdxc_engage_dma()
249 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar); in aml8726_sdxc_engage_dma()
283 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar); in aml8726_sdxc_disengage_dma()
290 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar); in aml8726_sdxc_disengage_dma()
308 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar); in aml8726_sdxc_disengage_dma()
426 CSR_WRITE_4(sc, AML_SDXC_IRQ_ENABLE_REG, ier); in aml8726_sdxc_start_command()
428 CSR_WRITE_4(sc, AML_SDXC_CNTRL_REG, ctlr); in aml8726_sdxc_start_command()
[all …]
HDaml8726_wdt.c100 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val)) macro
123 CSR_WRITE_4(sc, AML_WDT_RESET_REG, 0); in aml8726_wdt_watchdog()
124 CSR_WRITE_4(sc, AML_WDT_CTRL_REG, wcr); in aml8726_wdt_watchdog()
128 CSR_WRITE_4(sc, AML_WDT_CTRL_REG, in aml8726_wdt_watchdog()
149 CSR_WRITE_4(sc, AML_WDT_CTRL_REG, in aml8726_wdt_intr()
240 CSR_WRITE_4(sc, AML_WDT_CTRL_REG, in aml8726_wdt_attach()
300 CSR_WRITE_4(aml8726_wdt_sc, AML_WDT_RESET_REG, 0); in cpu_reset()
301 CSR_WRITE_4(aml8726_wdt_sc, AML_WDT_CTRL_REG, in cpu_reset()
HDaml8726_pic.c111 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val)) macro
126 CSR_WRITE_4(aml8726_pic_sc, AML_PIC_STAT_CLR_REG(nb), AML_PIC_BIT(nb)); in aml8726_pic_eoi()
167 CSR_WRITE_4(sc, AML_PIC_0_MASK_REG + i * 16, 0); in aml8726_pic_attach()
168 CSR_WRITE_4(sc, AML_PIC_0_STAT_CLR_REG + i * 16, ~0u); in aml8726_pic_attach()
169 CSR_WRITE_4(sc, AML_PIC_0_FIRQ_SEL + i * 16, 0); in aml8726_pic_attach()
255 CSR_WRITE_4(aml8726_pic_sc, AML_PIC_MASK_REG(nb), mask); in arm_mask_irq()
274 CSR_WRITE_4(aml8726_pic_sc, AML_PIC_MASK_REG(nb), mask); in arm_unmask_irq()
HDaml8726_timer.c130 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val)) macro
152 CSR_WRITE_4(sc, AML_TIMER_A_REG, sc->period_ticks); in aml8726_hardclock()
153 CSR_WRITE_4(sc, AML_TIMER_MUX_REG, in aml8726_hardclock()
196 CSR_WRITE_4(sc, AML_TIMER_A_REG, ticks); in aml8726_timer_start()
197 CSR_WRITE_4(sc, AML_TIMER_MUX_REG, in aml8726_timer_start()
214 CSR_WRITE_4(sc, AML_TIMER_MUX_REG, in aml8726_timer_stop()
257 CSR_WRITE_4(sc, AML_TIMER_MUX_REG, in aml8726_timer_attach()
264 CSR_WRITE_4(sc, AML_TIMER_E_REG, 0); in aml8726_timer_attach()
266 CSR_WRITE_4(sc, AML_TIMER_MUX_REG, in aml8726_timer_attach()
/freebsd-11-stable/sys/dev/jme/
HDif_jme.c227 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE | in jme_miibus_readreg()
258 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE | in jme_miibus_writereg()
371 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); in jme_eeprom_read_byte()
546 CSR_WRITE_4(sc, JME_PAR0, in jme_set_macaddr()
548 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]); in jme_set_macaddr()
616 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]); in jme_map_intr_vector()
617 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]); in jme_map_intr_vector()
618 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]); in jme_map_intr_vector()
619 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]); in jme_map_intr_vector()
1593 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & in jme_setwol()
[all …]
/freebsd-11-stable/sys/dev/tx/
HDif_tx.c355 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET); in epic_attach()
360 CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST); in epic_attach()
367 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F); in epic_attach()
715 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED); in epic_ifstart_locked()
874 CSR_WRITE_4(sc, INTSTAT, status); in epic_intr()
886 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED); in epic_intr()
955 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO); in epic_tx_underrun()
1051 CSR_WRITE_4(sc, MIICFG, sc->miicfg); in epic_ifmedia_upd_locked()
1110 CSR_WRITE_4(sc, MIICFG, sc->miicfg); in epic_ifmedia_upd_locked()
1126 CSR_WRITE_4(sc, MIICFG, sc->miicfg); in epic_ifmedia_upd_locked()
[all …]
/freebsd-11-stable/sys/dev/nge/
HDif_nge.c247 CSR_WRITE_4(sc, reg, \
251 CSR_WRITE_4(sc, reg, \
255 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
258 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
290 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); in nge_eeprom_idle()
407 CSR_WRITE_4(sc, NGE_MEAR, val); in nge_mii_bitbang_write()
498 CSR_WRITE_4(sc, reg, data); in nge_miibus_writereg()
602 CSR_WRITE_4(sc, NGE_CFG, reg); in nge_miibus_statchg()
607 CSR_WRITE_4(sc, NGE_CSR, reg); in nge_miibus_statchg()
631 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, in nge_miibus_statchg()
[all …]
/freebsd-11-stable/sys/dev/bge/
HDif_bge.c657 CSR_WRITE_4(sc, off, val); in bge_writemem_direct()
666 CSR_WRITE_4(sc, off, val); in bge_writembx()
1008 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); in bge_nvram_getbyte()
1019 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); in bge_nvram_getbyte()
1021 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); in bge_nvram_getbyte()
1022 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); in bge_nvram_getbyte()
1042 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); in bge_nvram_getbyte()
1045 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); in bge_nvram_getbyte()
1092 CSR_WRITE_4(sc, BGE_EE_ADDR, in bge_eeprom_getbyte()
1097 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); in bge_eeprom_getbyte()
[all …]
/freebsd-11-stable/sys/dev/dc/
HDif_dc.c363 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
366 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
389 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); in dc_eeprom_width()
431 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); in dc_eeprom_width()
449 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); in dc_eeprom_idle()
469 CSR_WRITE_4(sc, DC_SIO, 0x00000000); in dc_eeprom_idle()
521 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); in dc_eeprom_getword_pnic()
545 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); in dc_eeprom_getword_xircom()
548 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); in dc_eeprom_getword_xircom()
567 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); in dc_eeprom_getword()
[all …]
/freebsd-11-stable/sys/dev/bfe/
HDif_bfe.c682 CSR_WRITE_4(sc, BFE_RXCONF, flow); in bfe_miibus_statchg()
689 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); in bfe_miibus_statchg()
692 CSR_WRITE_4(sc, BFE_TX_CTRL, val); in bfe_miibus_statchg()
753 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); in bfe_list_rx_init()
868 CSR_WRITE_4(sc, BFE_SBINTVEC, val); in bfe_pci_setup()
872 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); in bfe_pci_setup()
884 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); in bfe_clear_stats()
911 CSR_WRITE_4(sc, BFE_IMASK, 0); in bfe_chip_halt()
914 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); in bfe_chip_halt()
917 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); in bfe_chip_halt()
[all …]
/freebsd-11-stable/sys/dev/sge/
HDif_sge.c182 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sge_res, reg, val) macro
217 CSR_WRITE_4(sc, ROMInterface, in sge_read_eeprom()
338 CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) | in sge_miibus_readreg()
362 CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) | in sge_miibus_writereg()
436 CSR_WRITE_4(sc, StationControl, ctl); in sge_miibus_statchg()
438 CSR_WRITE_4(sc, RGMIIDelay, 0x0441); in sge_miibus_statchg()
439 CSR_WRITE_4(sc, RGMIIDelay, 0x0440); in sge_miibus_statchg()
480 CSR_WRITE_4(sc, RxHashTable, hashes[0]); in sge_rxfilter()
481 CSR_WRITE_4(sc, RxHashTable2, hashes[1]); in sge_rxfilter()
507 CSR_WRITE_4(sc, IntrMask, 0); in sge_reset()
[all …]
/freebsd-11-stable/sys/dev/my/
HDif_my.c142 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
143 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
186 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); in my_send_cmd_to_phy()
190 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); in my_send_cmd_to_phy()
204 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); in my_send_cmd_to_phy()
207 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); in my_send_cmd_to_phy()
239 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); in my_phy_readreg()
248 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); in my_phy_readreg()
257 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); in my_phy_readreg()
284 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); in my_phy_writereg()
[all …]
/freebsd-11-stable/sys/dev/altera/atse/
HDif_atse.c321 #define CSR_WRITE_4(sc, reg, val) \ macro
508 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4); in atse_stop_locked()
563 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4); in atse_rxfilter_locked()
568 CSR_WRITE_4(sc, MHASH_START + i, 0x1); in atse_rxfilter_locked()
592 CSR_WRITE_4(sc, MHASH_START + i, in atse_rxfilter_locked()
766 CSR_WRITE_4(sc, BASE_CFG_MAC_0, v0); in atse_set_eth_address()
767 CSR_WRITE_4(sc, BASE_CFG_MAC_1, v1); in atse_set_eth_address()
770 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_0_0, v0); in atse_set_eth_address()
771 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_0_1, v1); in atse_set_eth_address()
774 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_1_0, v0); in atse_set_eth_address()
[all …]
/freebsd-11-stable/sys/dev/ale/
HDif_ale.c210 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in ale_miibus_readreg()
236 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in ale_miibus_writereg()
293 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); in ale_miibus_statchg()
367 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); in ale_get_macaddr()
375 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | in ale_get_macaddr()
1503 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); in ale_setwol()
1506 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); in ale_setwol()
1525 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); in ale_setwol()
1533 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); in ale_setwol()
1539 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); in ale_setwol()
[all …]
/freebsd-11-stable/sys/dev/age/
HDif_age.c218 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in age_miibus_readreg()
247 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in age_miibus_writereg()
347 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); in age_get_macaddr()
355 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | in age_get_macaddr()
389 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); in age_phy_reset()
391 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); in age_phy_reset()
1332 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); in age_setwol()
1425 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); in age_setwol()
1433 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_setwol()
1888 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_ioctl()
[all …]
/freebsd-11-stable/sys/dev/bwi/
HDbwimac.c125 CSR_WRITE_4(sc, BWI_MAC_TMPLT_CTRL, ofs); in bwi_tmplt_write_4()
126 CSR_WRITE_4(sc, BWI_MAC_TMPLT_DATA, val); in bwi_tmplt_write_4()
173 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, BWI_MOBJ_CTRL_VAL(obj_id, ofs)); in bwi_memobj_read_2()
187 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, BWI_MOBJ_CTRL_VAL(obj_id, ofs)); in bwi_memobj_read_4()
191 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, in bwi_memobj_read_4()
197 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, BWI_MOBJ_CTRL_VAL(obj_id, ofs)); in bwi_memobj_read_4()
216 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, BWI_MOBJ_CTRL_VAL(obj_id, ofs)); in bwi_memobj_write_2()
229 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, BWI_MOBJ_CTRL_VAL(obj_id, ofs)); in bwi_memobj_write_4()
232 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, in bwi_memobj_write_4()
236 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, BWI_MOBJ_CTRL_VAL(obj_id, ofs)); in bwi_memobj_write_4()
[all …]
/freebsd-11-stable/sys/dev/msk/
HDif_msk.c552 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); in msk_miibus_statchg()
634 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), in msk_setvlan()
636 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), in msk_setvlan()
639 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), in msk_setvlan()
641 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), in msk_setvlan()
1256 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); in msk_phy_power()
1301 CSR_WRITE_4(sc, B2_GP_IO, val); in msk_phy_power()
1359 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); in mskc_reset()
1368 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); in mskc_reset()
1422 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); in mskc_reset()
[all …]
/freebsd-11-stable/sys/dev/ipw/
HDif_ipwreg.h340 #define CSR_WRITE_4(sc, reg, val) \ macro
351 (CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)), \
355 (CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)), \
359 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
364 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
369 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
370 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \
374 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \

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