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Searched refs:COMBINE (Results 1 – 7 of 7) sorted by relevance

/freebsd-11-stable/sys/libkern/
HDqdivrem.c47 #define COMBINE(a, b) (((u_long)(a) << HALF_BITS) | (b)) macro
150 rbj = COMBINE(u[1] % t, u[2]);
152 rbj = COMBINE(rbj % t, u[3]);
154 rbj = COMBINE(rbj % t, u[4]);
158 tmp.ul[H] = COMBINE(q1, q2);
159 tmp.ul[L] = COMBINE(q3, q4);
213 u_long nn = COMBINE(uj0, uj1);
217 while (v2 * qhat > COMBINE(rhat, uj2)) {
266 tmp.ul[H] = COMBINE(uspace[1], uspace[2]);
267 tmp.ul[L] = COMBINE(uspace[3], uspace[4]);
[all …]
/freebsd-11-stable/lib/libc/quad/
HDqdivrem.c50 #define COMBINE(a, b) (((u_long)(a) << HALF_BITS) | (b)) macro
153 rbj = COMBINE(u[1] % t, u[2]);
155 rbj = COMBINE(rbj % t, u[3]);
157 rbj = COMBINE(rbj % t, u[4]);
161 tmp.ul[H] = COMBINE(q1, q2);
162 tmp.ul[L] = COMBINE(q3, q4);
216 u_long n = COMBINE(uj0, uj1);
220 while (v2 * qhat > COMBINE(rhat, uj2)) {
269 tmp.ul[H] = COMBINE(uspace[1], uspace[2]);
270 tmp.ul[L] = COMBINE(uspace[3], uspace[4]);
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp1696 case HexagonISD::COMBINE: return "HexagonISD::COMBINE"; in getTargetNodeName()
2044 SDValue Concat10 = DAG.getNode(HexagonISD::COMBINE, dl, in LowerVECTOR_SHUFFLE()
2051 SDValue Concat01 = DAG.getNode(HexagonISD::COMBINE, dl, in LowerVECTOR_SHUFFLE()
2322 return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, {H, L}); in buildVector64()
2439 ValR = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, in insertVector()
2587 return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, Op.getOperand(1), in LowerCONCAT_VECTORS()
2611 W = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, in LowerCONCAT_VECTORS()
2637 SDValue WW = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, in LowerCONCAT_VECTORS()
HDHexagonISelLowering.h54 COMBINE, enumerator
HDHexagonISelLoweringHVX.cpp808 SDValue WW = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, {W1, W0}); in extractHvxSubvectorReg()
871 SDValue Vec64 = DAG.getNode(HexagonISD::COMBINE, dl, MVT::v8i8, {W1, W0}); in extractHvxSubvectorPred()
HDHexagonPatterns.td998 def HexagonCOMBINE: SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
/freebsd-11-stable/contrib/llvm-project/clang/include/clang/Basic/
HDarm_neon.td891 def COMBINE : NoTestOpInst<"vcombine", "Q..", "dPl", OP_CONC>;