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Searched refs:AllocateReg (Results 1 – 16 of 16) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMCallingConv.cpp27 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
42 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
72 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList); in f64AssignAAPCS()
76 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
95 unsigned T = State.AllocateReg(LoRegList[i]); in f64AssignAAPCS()
122 unsigned Reg = State.AllocateReg(HiRegList, LoRegList); in f64RetAssign()
209 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
252 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); in CC_ARM_AAPCS_Custom_Aggregate()
263 State.AllocateReg(Reg); in CC_ARM_AAPCS_Custom_Aggregate()
HDARMISelLowering.cpp2496 unsigned Reg = State->AllocateReg(GPRArgRegs); in HandleByVal()
2503 Reg = State->AllocateReg(GPRArgRegs); in HandleByVal()
2516 while (State->AllocateReg(GPRArgRegs)) in HandleByVal()
2533 State->AllocateReg(GPRArgRegs); in HandleByVal()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
HDPPCCallingConv.cpp49 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
74 State.AllocateReg(ArgRegs[RegNum + i]); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
98 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
118 unsigned Reg = State.AllocateReg(HiRegList); in CC_PPC32_SPE_CustomSplitFP64()
127 unsigned T = State.AllocateReg(LoRegList[i]); in CC_PPC32_SPE_CustomSplitFP64()
147 unsigned Reg = State.AllocateReg(HiRegList, LoRegList); in CC_PPC32_SPE_RetF64()
HDPPCISelLowering.cpp6918 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) { in CC_AIX()
6938 if (unsigned Reg = State.AllocateReg(FPR)) in CC_AIX()
6948 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) { in CC_AIX()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86CallingConv.cpp53 unsigned Reg = State.AllocateReg(AvailableRegs[I]); in CC_X86_32_RegCall_Assign2Regs()
104 unsigned AssigedReg = State.AllocateReg(Reg); in CC_X86_VectorCallAssignRegister()
149 (void)State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT)); in CC_X86_64_VectorCall()
157 (void)State.AllocateReg(CC_X86_64_VectorCallGetGPRs()); in CC_X86_64_VectorCall()
160 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) { in CC_X86_64_VectorCall()
211 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) { in CC_X86_32_VectorCall()
261 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_X86_32_MCUInReg()
282 It.convertToReg(State.AllocateReg(RegList[FirstFree++])); in CC_X86_32_MCUInReg()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDAMDGPUCallLowering.cpp394 CCInfo.AllocateReg(PrivateSegmentBufferReg); in allocateHSAUserSGPRs()
400 CCInfo.AllocateReg(DispatchPtrReg); in allocateHSAUserSGPRs()
406 CCInfo.AllocateReg(QueuePtrReg); in allocateHSAUserSGPRs()
417 CCInfo.AllocateReg(InputPtrReg); in allocateHSAUserSGPRs()
423 CCInfo.AllocateReg(DispatchIDReg); in allocateHSAUserSGPRs()
429 CCInfo.AllocateReg(FlatScratchInitReg); in allocateHSAUserSGPRs()
602 CCInfo.AllocateReg(ImplicitBufferPtrReg); in lowerFormalArguments()
678 CCInfo.AllocateReg(AMDGPU::VGPR0); in lowerFormalArguments()
679 CCInfo.AllocateReg(AMDGPU::VGPR1); in lowerFormalArguments()
721 CCInfo.AllocateReg(Info->getScratchRSrcReg()); in lowerFormalArguments()
[all …]
HDSIISelLowering.cpp1634 CCInfo.AllocateReg(Reg); in allocateSpecialEntryInputVGPRs()
1642 CCInfo.AllocateReg(Reg); in allocateSpecialEntryInputVGPRs()
1650 CCInfo.AllocateReg(Reg); in allocateSpecialEntryInputVGPRs()
1675 Reg = CCInfo.AllocateReg(Reg); in allocateVGPR32Input()
1693 Reg = CCInfo.AllocateReg(Reg); in allocateSGPR32InputImpl()
1774 CCInfo.AllocateReg(ImplicitBufferPtrReg); in allocateHSAUserSGPRs()
1781 CCInfo.AllocateReg(PrivateSegmentBufferReg); in allocateHSAUserSGPRs()
1787 CCInfo.AllocateReg(DispatchPtrReg); in allocateHSAUserSGPRs()
1793 CCInfo.AllocateReg(QueuePtrReg); in allocateHSAUserSGPRs()
1799 CCInfo.AllocateReg(InputPtrReg); in allocateHSAUserSGPRs()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDCallingConvLower.h354 unsigned AllocateReg(unsigned Reg) { in AllocateReg() function
361 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { in AllocateReg() function
371 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() function
412 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg() function
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
HDSystemZCallingConv.h110 unsigned Reg = State.AllocateReg(SystemZ::ArgGPRs); in CC_SystemZ_I128Indirect()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64CallingConvention.cpp147 State.AllocateReg(Reg); in CC_AArch64_Custom_Block()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
HDRISCVISelLowering.cpp1461 if (Register Reg = State.AllocateReg(ArgGPRs)) { in CC_RISCVAssign2XLen()
1478 if (Register Reg = State.AllocateReg(ArgGPRs)) { in CC_RISCVAssign2XLen()
1559 State.AllocateReg(ArgGPRs); in CC_RISCV()
1578 Register Reg = State.AllocateReg(ArgGPRs); in CC_RISCV()
1586 if (!State.AllocateReg(ArgGPRs)) in CC_RISCV()
1622 Reg = State.AllocateReg(ArgFPR32s, ArgFPR64s); in CC_RISCV()
1624 Reg = State.AllocateReg(ArgFPR64s, ArgFPR32s); in CC_RISCV()
1626 Reg = State.AllocateReg(ArgGPRs); in CC_RISCV()
1865 if (unsigned Reg = State.AllocateReg(GPRList)) { in CC_RISCV_FastCC()
1877 if (unsigned Reg = State.AllocateReg(FPR32List)) { in CC_RISCV_FastCC()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsISelLowering.cpp2914 Reg = State.AllocateReg(FloatVectorIntRegs); in CC_MipsO32()
2916 State.AllocateReg(Mips::A1); in CC_MipsO32()
2918 State.AllocateReg(Mips::A3); in CC_MipsO32()
2922 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2926 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2930 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2935 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2937 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2938 State.AllocateReg(IntRegs); in CC_MipsO32()
2943 Reg = State.AllocateReg(F32Regs); in CC_MipsO32()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
HDMSP430ISelLowering.cpp530 unsigned Reg = State.AllocateReg(RegList); in AnalyzeArguments()
538 unsigned Reg = State.AllocateReg(RegList); in AnalyzeArguments()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp62 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_Sparc_Assign_Split_64()
73 if (unsigned Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Split_64()
91 if (unsigned Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
97 if (unsigned Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
HDAVRISelLowering.cpp982 unsigned Reg = CCInfo.AllocateReg( in analyzeStandardArguments()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp144 State.AllocateReg(ArgRegs[RegNum]); in CC_SkipOdd()