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Searched refs:AVX512 (Results 1 – 7 of 7) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
HDVFABIDemangling.cpp41 .Case("e", VFISAKind::AVX512) in tryParseISA()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86InstrFormats.td232 // Specify AVX512 8-bit compressed displacement encoding based on the vector
322 // The scaling factor for AVX512's compressed displacement is either
326 // Possible values are: 0 (non-AVX512 inst), 1, 2, 4, 8, 16, 32 and 64.
493 // SI - SSE 1 & 2 scalar intrinsics - vex form available on AVX512
509 // SIi8 - SSE 1 & 2 scalar instructions - vex form available on AVX512
861 class AVX512<bits<8> o, Format F, dag outs, dag ins, string asm,
HDX86.td203 "Promote selected AES instructions to AVX512/AVX registers",
391 "Prefer AVX512 mask registers over PTEST/MOVMSK">;
626 // Skylake-AVX512
HDX86InstrAVX512.td1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
9 // This file describes the X86 AVX512 instruction set, defining the
189 def NAME: AVX512<O, F, Outs, Ins,
196 def NAME#k: AVX512<O, F, Outs, MaskingIns,
208 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
369 def NAME: AVX512<O, F, Outs, Ins,
374 def NAME#k: AVX512<O, F, Outs, MaskingIns,
2069 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
2647 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
2653 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
HDVectorUtils.h50 AVX512, // x86 AVX512 enumerator
/freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/
HDTargetInfo.cpp2039 AVX512 enumerator
2045 case X86AVXABILevel::AVX512: in getNativeVectorSizeForAVXABI()
10002 ? X86AVXABILevel::AVX512 in getTargetCodeGenInfo()
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/
HDIntrinsicsX86.td2626 // AVX512
3864 // AVX512 gather/scatter intrinsics that use vXi1 masks.