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Searched refs:AR_CR (Results 1 – 20 of 20) sorted by relevance

/freebsd-11-stable/sys/dev/ath/ath_hal/ar5211/
HDar5211_recv.c59 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); in ar5211EnableReceive()
68 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ in ar5211StopDmaReceive()
69 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) { in ar5211StopDmaReceive()
74 , OS_REG_READ(ah, AR_CR) in ar5211StopDmaReceive()
HDar5211reg.h32 #define AR_CR 0x0008 /* control register */ macro
/freebsd-11-stable/sys/dev/ath/ath_hal/ar5210/
HDar5210_recv.c58 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); in ar5210EnableReceive()
69 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ in ar5210StopDmaReceive()
71 if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) in ar5210StopDmaReceive()
77 ath_hal_printf(ah, "AR_CR=0x%x\n", OS_REG_READ(ah, AR_CR)); in ar5210StopDmaReceive()
HDar5210_xmit.c300 if (OS_REG_READ(ah, AR_CR) & AR_CR_TXE0) in ar5210SetTxDP()
302 __func__, OS_REG_READ(ah, AR_CR)); in ar5210SetTxDP()
378 OS_REG_WRITE(ah, AR_CR, AR_CR_TXE0); in ar5210StartTxDma()
381 OS_REG_WRITE(ah, AR_CR, AR_CR_TXE1); /* enable altq xmit */ in ar5210StartTxDma()
440 OS_REG_WRITE(ah, AR_CR, AR_CR_TXD0); in ar5210StopTxDma()
446 OS_REG_WRITE(ah, AR_CR, 0); in ar5210StopTxDma()
HDar5210reg.h36 #define AR_CR 0x0008 /* Command register */ macro
/freebsd-11-stable/sys/dev/ath/ath_hal/ar5212/
HDar5212_recv.c58 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); in ar5212EnableReceive()
68 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ in ar5212StopDmaReceive()
69 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) { in ar5212StopDmaReceive()
75 OS_REG_READ(ah, AR_CR), in ar5212StopDmaReceive()
HDar5212reg.h27 #define AR_CR 0x0008 /* MAC control register */ macro
HDar5212_reset.c1142 OS_REG_SET_BIT(ah, AR_CR, AR_CR_RXD); in ar5212MacStop()
1155 if (!OS_REG_IS_BIT_SET(ah, AR_CR, AR_CR_RXE)) { in ar5212MacStop()
/freebsd-11-stable/sys/contrib/dev/ath/ath_hal/ar9300/
HDar9300_recv.c61 OS_REG_WRITE(ah, AR_CR, 0); in ar9300_enable_receive()
138 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); in ar9300_stop_dma_receive()
142 if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) { in ar9300_stop_dma_receive()
153 OS_REG_READ(ah, AR_CR), in ar9300_stop_dma_receive()
HDar9300_power.c990 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ in ar9300_set_power_mode_wow_sleep()
991 if (!ath_hal_waitfor(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) { in ar9300_set_power_mode_wow_sleep()
994 OS_REG_READ(ah, AR_CR), OS_REG_READ(ah, AR_DIAG_SW)); in ar9300_set_power_mode_wow_sleep()
HDar9300_tx99_tgt.c506 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); // set receive disable in ar9300_tx99_tgt_start()
HDar9300_xmit_ds.c492 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ in ar9300__cont_tx_mode()
HDar9300_misc.c1381 ath_hal_printf(ah, "AR_CR 0x%x \n", OS_REG_READ(ah, AR_CR)); in ar9300_dma_reg_dump()
3816 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ in ar9300_tx99_start()
HDar9300reg.h33 #define AR_CR AR_MAC_DMA_OFFSET(MAC_DMA_CR) macro
HDar9300_reset.c2059 (OS_REG_READ(ah, AR_CR) & AR_CR_RXE)) { in ar9300_chip_reset()
/freebsd-11-stable/sys/dev/ath/ath_hal/ar5416/
HDar5416_recv.c78 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ in ar5416StopDmaReceive()
79 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) { in ar5416StopDmaReceive()
85 OS_REG_READ(ah, AR_CR), in ar5416StopDmaReceive()
/freebsd-11-stable/tools/tools/ath/common/
HDdumpregs_5210.c46 DEFBASICfmt(AR_CR, "CR", AR_CR_BITS),
HDdumpregs_5211.c44 DEFBASICfmt(AR_CR, "CR", AR_CR_BITS),
HDdumpregs_5212.c47 DEFBASIC(AR_CR, "CR"),
HDdumpregs_5416.c46 DEFBASIC(AR_CR, "CR"),