Searched refs:AR934X_PLL_ETH_XMII_CONTROL_REG (Results 1 – 2 of 2) sorted by relevance
69 #define AR934X_PLL_ETH_XMII_CONTROL_REG (AR71XX_PLL_CPU_BASE + 0x2c) macro
249 ATH_WRITE_REG(AR934X_PLL_ETH_XMII_CONTROL_REG, pll); in ar934x_chip_set_pll_ge()