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Searched refs:AL_REG_FIELD_SET (Results 1 – 7 of 7) sorted by relevance

/freebsd-11-stable/sys/contrib/alpine-hal/eth/
HDal_hal_eth_kr.c377 AL_REG_FIELD_SET(cfg_lane_0, in al_eth_an_lt_unit_config()
381 AL_REG_FIELD_SET(cfg_lane_0, in al_eth_an_lt_unit_config()
391 AL_REG_FIELD_SET(cfg_lane_0, in al_eth_an_lt_unit_config()
395 AL_REG_FIELD_SET(cfg_lane_0, in al_eth_an_lt_unit_config()
405 AL_REG_FIELD_SET(cfg_lane_0, in al_eth_an_lt_unit_config()
409 AL_REG_FIELD_SET(cfg_lane_0, in al_eth_an_lt_unit_config()
415 AL_REG_FIELD_SET(cfg_lane_1, in al_eth_an_lt_unit_config()
419 AL_REG_FIELD_SET(cfg_lane_1, in al_eth_an_lt_unit_config()
425 AL_REG_FIELD_SET(cfg_lane_2, in al_eth_an_lt_unit_config()
429 AL_REG_FIELD_SET(cfg_lane_2, in al_eth_an_lt_unit_config()
[all …]
HDal_hal_eth_main.c1714 AL_REG_FIELD_SET(val, ETH_10G_MAC_MDIO_CFG_HOLD_TIME_MASK, in al_eth_mdio_config()
2421 AL_REG_FIELD_SET(reg, EC_RFW_HDR_SPLIT_DEF_LEN_MASK, EC_RFW_HDR_SPLIT_DEF_LEN_SHIFT, header_len); in al_eth_rx_header_split_config()
2599 AL_REG_FIELD_SET(val, AL_FIELD_MASK(3,0), 0, entry->prio_sel); in al_eth_fwd_ctrl_entry_to_val()
2600 AL_REG_FIELD_SET(val, AL_FIELD_MASK(7,4), 4, entry->queue_sel_1); in al_eth_fwd_ctrl_entry_to_val()
2601 AL_REG_FIELD_SET(val, AL_FIELD_MASK(9,8), 8, entry->queue_sel_2); in al_eth_fwd_ctrl_entry_to_val()
2602 AL_REG_FIELD_SET(val, AL_FIELD_MASK(13,10), 10, entry->udma_sel); in al_eth_fwd_ctrl_entry_to_val()
2603 AL_REG_FIELD_SET(val, AL_FIELD_MASK(17,15), 15, entry->hdr_split_len_sel); in al_eth_fwd_ctrl_entry_to_val()
2792 AL_REG_FIELD_SET(val, AL_FIELD_MASK(3,0), 0, udma_mask); in al_eth_fwd_mhash_table_set()
2793 AL_REG_FIELD_SET(val, AL_FIELD_MASK(5,4), 4, qid); in al_eth_fwd_mhash_table_set()
2804 AL_REG_FIELD_SET(val, AL_FIELD_MASK(5,2), 2, entry->udma_mask); in al_eth_fwd_vid_entry_to_val()
[all …]
/freebsd-11-stable/sys/contrib/alpine-hal/
HDal_hal_iofic.c77 AL_REG_FIELD_SET(reg, in al_iofic_moder_res_config()
99 AL_REG_FIELD_SET(reg, in al_iofic_legacy_moder_interval_config()
122 AL_REG_FIELD_SET(reg, in al_iofic_msix_moder_interval_config()
143 AL_REG_FIELD_SET(reg, in al_iofic_msix_vmid_attributes_config()
HDal_hal_reg_utils.h68 #define AL_REG_FIELD_SET(reg, mask, shift, val) \ macro
88 AL_REG_FIELD_SET(reg, AL_BIT(shift), shift, val)
HDal_hal_serdes.c1715 AL_REG_FIELD_SET(reg, in al_serdes_tx_advanced_params_set()
1720 AL_REG_FIELD_SET(reg, in al_serdes_tx_advanced_params_set()
1732 AL_REG_FIELD_SET(reg, in al_serdes_tx_advanced_params_set()
1737 AL_REG_FIELD_SET(reg, in al_serdes_tx_advanced_params_set()
1749 AL_REG_FIELD_SET(reg, in al_serdes_tx_advanced_params_set()
1754 AL_REG_FIELD_SET(reg, in al_serdes_tx_advanced_params_set()
1831 AL_REG_FIELD_SET(reg, in al_serdes_rx_advanced_params_set()
1836 AL_REG_FIELD_SET(reg, in al_serdes_rx_advanced_params_set()
1848 AL_REG_FIELD_SET(reg, in al_serdes_rx_advanced_params_set()
1853 AL_REG_FIELD_SET(reg, in al_serdes_rx_advanced_params_set()
[all …]
HDal_hal_pcie.c404 AL_REG_FIELD_SET(reg, 0xFFFF, 0, lat_rply_timers->round_trip_lat_limit); in al_pcie_port_lat_rply_timers_config()
405 AL_REG_FIELD_SET(reg, 0xFFFF0000, 16, lat_rply_timers->replay_timer_limit); in al_pcie_port_lat_rply_timers_config()
612 AL_REG_FIELD_SET(reg, PCIE_PORT_GEN3_EQ_LF_MASK, in al_pcie_port_gen3_params_config()
615 AL_REG_FIELD_SET(reg, PCIE_PORT_GEN3_EQ_FS_MASK, in al_pcie_port_gen3_params_config()
622 AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_LF_MASK, in al_pcie_port_gen3_params_config()
625 AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_FS_MASK, in al_pcie_port_gen3_params_config()
1352 AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_MASK, in al_pcie_port_operating_mode_config()
2233 AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_MASK, in al_pcie_target_bus_set()
2236 AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_BUSNUM_MASK, in al_pcie_target_bus_set()
2356 AL_REG_FIELD_SET(reg, 0xF, 0, atu_region->index); in al_pcie_atu_region_set()
[all …]
HDal_hal_udma_config.c993 …AL_REG_FIELD_SET(reg, UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_MASK, UDMA_S2M_WR_DATA_CFG_2_DESC_WAI… in al_udma_s2m_no_desc_cfg_set()