Searched refs:AFGR64RegClass (Results 1 – 10 of 10) sorted by relevance
51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()70 const MCRegisterClass *AFGR64RegClass; variable
183 for (MCPhysReg Reg : Mips::AFGR64RegClass) in getReservedRegs()
319 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandBuildPairF64()384 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandExtractElementF64()462 if (Mips::AFGR64RegClass.contains(Reg)) { in emitPrologue()
145 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()268 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()346 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
400 const TargetRegisterClass *RC = &Mips::AFGR64RegClass; in materializeFP()785 ResultReg = createResultReg(&Mips::AFGR64RegClass); in emitLoad()1012 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass); in selectFPExt()1041 RC = &Mips::AFGR64RegClass; in selectSelect()1448 Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++); in fastLowerArguments()
340 unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8; in printSavedRegsBitmask()353 } else if (Mips::AFGR64RegClass.contains(Reg)) { in printSavedRegsBitmask()
131 return STI.isFP64bit() ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in getRegClassForTypeOnBank()
4059 if (RC == &Mips::AFGR64RegClass) { in parseRegForInlineAsmConstraint()4113 return std::make_pair(0U, &Mips::AFGR64RegClass); in getRegForInlineAsmConstraint()
179 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); in MipsSETargetLowering()
88 AFGR64RegClass->contains(SubReg) || in SetPhysRegUsed()