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Searched refs:xlr_reg_t (Results 1 – 13 of 13) sorted by relevance

/freebsd-10-stable/sys/mips/rmi/
Dpic.h162 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); in pic_read_control()
174 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); in pic_write_control()
184 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); in pic_update_control()
194 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); in pic_ack()
202 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); in pic_send_ipi()
213 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); in pic_setup_intr()
225 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); in pic_init_timer()
238 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); in pic_set_timer()
249 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); in pic_timer_count32()
261 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); in pic_timer_count()
Diomap.h105 typedef volatile __uint32_t xlr_reg_t; typedef
108 #define xlr_io_mmio(offset) ((xlr_reg_t *)(xlr_io_base+(offset)))
Dboard.c62 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); in xlr_pcmcia_present()
186 xlr_reg_t *gpio_mmio = in quad0_xaui()
197 xlr_reg_t *gpio_mmio = in quad1_xaui()
276 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); in xls_board_specific_overrides()
Dxlr_machdep.c307 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); in xlr_pic_init()
522 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); in platform_reset()
Diodi.c90 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_FLASH_OFFSET); in bridge_pcmcia_ack()
Dxlr_i2c.c111 xlr_reg_t *iobase_i2c_regs;
Dxlr_pci.c436 xlr_reg_t *pcie_mmio_le = xlr_io_mmio(XLR_IO_PCIE_1_OFFSET); in bridge_pcie_ack()
/freebsd-10-stable/sys/mips/rmi/dev/nlge/
Dif_nlge.c186 static int nlge_mii_read_internal(xlr_reg_t *mii_base, int phyaddr,
188 static void nlge_mii_write_internal(xlr_reg_t *mii_base, int phyaddr,
226 static void dump_reg(xlr_reg_t *addr, uint32_t offset, char *name);
228 static void dump_na_registers(xlr_reg_t *base, int port_id);
1074 nlna_config_spill(xlr_reg_t *base, int reg_start_0, int reg_start_1, in nlna_config_spill()
1394 xlr_reg_t *addr; in nlna_reset_ports()
1495 xlr_reg_t *base; in nlge_port_disable()
1540 xlr_reg_t *base; in nlge_port_enable()
1594 xlr_reg_t *mmio_gpio; in nlge_sgmii_init()
1647 xlr_reg_t *base; in nlge_intr()
[all …]
Dif_nlge.h1112 xlr_reg_t *base;
1140 xlr_reg_t *base;
1141 xlr_reg_t *mii_base;
1142 xlr_reg_t *pcs_addr;
1143 xlr_reg_t *serdes_addr;
/freebsd-10-stable/sys/mips/rmi/dev/xlr/
Drge.c728 xlr_reg_t *mii_mmio = priv->mii_mmio; in rmi_xlr_mac_mii_init()
747 rge_mii_read_internal(xlr_reg_t * mii_mmio, int phyaddr, int regidx) in rge_mii_read_internal()
839 rge_mii_write_internal(xlr_reg_t * mii_mmio, int phyaddr, int regidx, int regval) in rge_mii_write_internal()
875 xlr_reg_t *mmio_gpio = (xlr_reg_t *) (xlr_io_base + XLR_IO_GPIO_OFFSET); in serdes_regs_init()
1064 xlr_reg_t *mmio = priv->mmio; in rmi_xlr_gmac_config_speed()
1126 xlr_reg_t *mmio = priv->mmio; in rmi_xlr_xgmac_init()
1224 xlr_reg_t *mmio = priv->mmio; in rmi_xlr_gmac_reset()
1273 xlr_reg_t *mmio = priv->mmio; in rmi_xlr_gmac_init()
1745 priv->mmio = (xlr_reg_t *) (xlr_io_base + gmac_conf->baseaddr + in rge_attach()
1751 priv->mmio = (xlr_reg_t *) (xlr_io_base + gmac_conf->baseaddr); in rge_attach()
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Drge.h1002 xlr_reg_t *mmio;
1003 xlr_reg_t *mii_mmio;
1004 xlr_reg_t *pcs_mmio;
1005 xlr_reg_t *serdes_mmio;
/freebsd-10-stable/sys/mips/rmi/dev/sec/
Drmilib.h643 xlr_reg_t *mmio;
Drmilib.c107 xlr_reg_t *mmio; in xlr_sec_init()