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/freebsd-10-stable/crypto/openssl/crypto/evp/
Devptests.txt16 # AES 128 ECB tests (from FIPS-197 test vectors, encrypt)
20 # AES 192 ECB tests (from FIPS-197 test vectors, encrypt)
24 # AES 256 ECB tests (from FIPS-197 test vectors, encrypt)
28 # AES 128 ECB tests (from NIST test vectors, encrypt)
32 # AES 128 ECB tests (from NIST test vectors, decrypt)
36 # AES 192 ECB tests (from NIST test vectors, decrypt)
40 # AES 256 ECB tests (from NIST test vectors, decrypt)
44 # AES 128 CBC tests (from NIST test vectors, encrypt)
48 # AES 192 CBC tests (from NIST test vectors, encrypt)
52 # AES 256 CBC tests (from NIST test vectors, encrypt)
[all …]
/freebsd-10-stable/sys/crypto/siphash/
Dsiphash_test.c39 uint8_t vectors[64][8] = variable
129 if (memcmp(out, vectors[i], 8)) in SipHash24_TestVectors()
/freebsd-10-stable/sys/dev/cxgbe/firmware/
Dt4fw_cfg.txt46 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
81 # It gets 32 MSI/128 MSI-X vectors.
113 # PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
119 # PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
Dt5fw_cfg.txt90 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
125 # It gets 32 MSI/128 MSI-X vectors.
158 # PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
164 # PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
Dt6fw_cfg.txt88 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
143 # It gets 32 MSI/128 MSI-X vectors.
174 # PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
180 # PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
/freebsd-10-stable/sys/dev/acpica/
Dacpi_hpet.c108 uint32_t vectors; member
497 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); in hpet_attach()
501 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, in hpet_attach()
544 sc->t[0].vectors = 0; in hpet_attach()
545 sc->t[1].vectors = 0; in hpet_attach()
610 else if (dvectors & t->vectors) { in hpet_attach()
611 t->irq = ffs(dvectors & t->vectors) - 1; in hpet_attach()
634 if (t->irq < 0 && (cvectors & t->vectors) != 0) { in hpet_attach()
635 cvectors &= t->vectors; in hpet_attach()
713 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) in hpet_attach()
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/X86/
DX86CallingConv.td46 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3
52 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3
103 // 256-bit FP vectors
108 // 512-bit FP vectors
270 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
274 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
290 // 128 bit vectors are passed by pointer
294 // 256 bit vectors are passed by pointer
297 // 512 bit vectors are passed by pointer
416 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
[all …]
/freebsd-10-stable/contrib/llvm/include/llvm/IR/
DIntrinsicsARM.td158 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
282 // The shift counts for these intrinsics are always vectors, even for constant
412 // Source operands are: the address, the N input vectors (since only one
432 // Source operands are: the address, the N vectors, and the alignment.
451 // Source operands are: the address, the N vectors, the lane number, and
DIntrinsicsPowerPC.td61 /// vectors and returns one. These intrinsics have no side effects.
68 /// vectors and returns one. These intrinsics have no side effects.
75 /// vectors and returns one. These intrinsics have no side effects.
82 /// vectors and returns one. These intrinsics have no side effects.
DInstruction.def172 HANDLE_OTHER_INST(56, ShuffleVector, ShuffleVectorInst) // shuffle two vectors.
/freebsd-10-stable/contrib/gcc/
Dmode-classes.def31 DEF_MODE_CLASS (MODE_VECTOR_INT), /* SIMD vectors */ \
/freebsd-10-stable/sys/dev/pci/
Dpcivar.h475 pci_remap_msix(device_t dev, int count, const u_int *vectors) in pci_remap_msix() argument
477 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); in pci_remap_msix()
Dvga_pci.c513 const u_int *vectors) in vga_pci_remap_msix() argument
520 return (pci_remap_msix(dev, count, vectors)); in vga_pci_remap_msix()
Dpci_private.h98 int count, const u_int *vectors);
Dpci_if.m171 const u_int *vectors;
Dpci.c1686 const u_int *vectors) in pci_remap_msix_method() argument
1703 if (vectors[i] > msix->msix_alloc) in pci_remap_msix_method()
1714 if (vectors[i] != 0) in pci_remap_msix_method()
1715 used[vectors[i] - 1] = 1; in pci_remap_msix_method()
1753 msix->msix_table[i].mte_vector = vectors[i]; in pci_remap_msix_method()
1778 if (vectors[i] == 0) in pci_remap_msix_method()
1780 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; in pci_remap_msix_method()
1790 if (vectors[i] == 0) in pci_remap_msix_method()
1794 msix->msix_vectors[vectors[i] - 1].mv_irq); in pci_remap_msix_method()
/freebsd-10-stable/sys/arm/arm/
Dmachdep.c302 unsigned int *vectors = (int *) va; in arm_vector_init() local
303 unsigned int *vectors_data = vectors + (page0_data - page0); in arm_vector_init()
315 vectors[vec] = page0[vec]; in arm_vector_init()
/freebsd-10-stable/contrib/llvm/tools/clang/include/clang/Basic/
Darm_neon.td217 // 2,3,4: array of default vectors
417 // E.3.20 Combining vectors
421 // E.3.21 Splitting vectors
428 // E.3.22 Converting vectors
695 // Converting vectors
820 // Converting vectors
889 // Combining vectors, with additional Pl
958 // Across vectors class
/freebsd-10-stable/contrib/llvm/patches/
Dpatch-r262261-llvm-r199187-sparc.diff10 xmm registers can hold f32, f64, and 128-bit vectors. The three
/freebsd-10-stable/sys/dev/ixl/
Dif_ixlv.c1146 int rid, want, vectors, queues, available; in ixlv_init_msix() local
1187 vectors = want; in ixlv_init_msix()
1216 if (pci_alloc_msix(dev, &vectors) == 0) { in ixlv_init_msix()
1218 "Using MSIX interrupts with %d vectors\n", vectors); in ixlv_init_msix()
1219 sc->msix = vectors; in ixlv_init_msix()
1260 return (vectors); in ixlv_init_msix()
Dif_ixl.c2096 int rid, want, vectors, queues, available; in ixl_init_msix() local
2161 vectors = want; in ixl_init_msix()
2170 if (pci_alloc_msix(dev, &vectors) == 0) { in ixl_init_msix()
2172 "Using MSIX interrupts with %d vectors\n", vectors); in ixl_init_msix()
2173 pf->msix = vectors; in ixl_init_msix()
2194 return (vectors); in ixl_init_msix()
2197 vectors = pci_msi_count(dev); in ixl_init_msix()
2202 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) in ixl_init_msix()
2208 return (vectors); in ixl_init_msix()
/freebsd-10-stable/contrib/gcc/doc/
Dcfg.texi100 In addition to notes, the jump table vectors are also represented as
101 ``pseudo-instructions'' inside the insn stream. These vectors never
105 address and referencing the vector, so cleaning up these vectors is
106 postponed until after liveness analysis. Thus the jump table vectors
149 type point to type-safe vectors of edges to the predecessors and
/freebsd-10-stable/sys/dev/ntb/ntb_hw/
Dntb_hw.c1021 u_int *vectors; in intel_ntb_remap_msix() local
1028 vectors = malloc(desired * sizeof(*vectors), M_NTB, M_ZERO | M_WAITOK); in intel_ntb_remap_msix()
1031 vectors[i] = (i % avail) + 1; in intel_ntb_remap_msix()
1033 rc = pci_remap_msix(dev, desired, vectors); in intel_ntb_remap_msix()
1034 free(vectors, M_NTB); in intel_ntb_remap_msix()
/freebsd-10-stable/crypto/openssl/crypto/rc4/
Drrc4.doc125 of genuine RC4 as found in BSAFE. I chose a set of test vectors
134 The vectors I used (together with the ciphertext they produce)
/freebsd-10-stable/sys/dev/drm/
Dradeon_drm.h198 } vectors; member

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