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Searched refs:v2i64 (Results 1 – 25 of 36) sorted by relevance

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/freebsd-10-stable/contrib/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp189 { ISD::SHL, MVT::v2i64, 1 }, in getArithmeticInstrCost()
190 { ISD::SRL, MVT::v2i64, 1 }, in getArithmeticInstrCost()
230 { ISD::SHL, MVT::v2i64, 1 }, // psllq. in getArithmeticInstrCost()
235 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. in getArithmeticInstrCost()
262 { ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized. in getArithmeticInstrCost()
267 { ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized. in getArithmeticInstrCost()
272 { ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized. in getArithmeticInstrCost()
283 { ISD::SDIV, MVT::v2i64, 2*20 }, in getArithmeticInstrCost()
287 { ISD::UDIV, MVT::v2i64, 2*20 }, in getArithmeticInstrCost()
324 { ISD::MUL, MVT::v2i64, 9 }, in getArithmeticInstrCost()
[all …]
DX86InstrSSE.td290 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
291 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
303 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
331 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
332 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
333 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
334 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
335 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
336 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
341 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
[all …]
DX86InstrFragmentsSIMD.td278 // NOTE: all 128-bit integer vector loads are promoted to v2i64
281 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
344 // NOTE: all 128-bit integer vector loads are promoted to v2i64
350 (v2i64 (alignedload node:$ptr))>;
396 // NOTE: all 128-bit integer vector loads are promoted to v2i64
399 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
454 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
467 (bitconvert (v2i64 (X86vzmovl
468 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
474 (bitconvert (v2i64 (X86vzload node:$src)))>;
DX86CallingConv.td43 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
100 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
237 CCPromoteToType<v2i64>>>>,
240 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
268 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
291 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
317 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
339 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
408 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
417 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
[all …]
DX86InstrAVX512.td18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
[all …]
DX86ISelLowering.cpp938 addRegisterClass(MVT::v2i64, &X86::VR128RegClass); in resetOperationActions()
943 setOperationAction(ISD::ADD, MVT::v2i64, Legal); in resetOperationActions()
945 setOperationAction(ISD::MUL, MVT::v2i64, Custom); in resetOperationActions()
949 setOperationAction(ISD::SUB, MVT::v2i64, Legal); in resetOperationActions()
959 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); in resetOperationActions()
971 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) { in resetOperationActions()
985 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); in resetOperationActions()
987 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); in resetOperationActions()
992 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); in resetOperationActions()
993 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); in resetOperationActions()
[all …]
DX86InstrMMX.td276 (i64 (vector_extract (v2i64 VR128:$src),
283 (v2i64
583 [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>;
DX86RegisterInfo.td436 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
461 def VR128X : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
/freebsd-10-stable/contrib/llvm/lib/Target/R600/
DAMDILISelLowering.cpp58 (int)MVT::v2i64 in InitAMDILLowering()
83 (int)MVT::v2i64 in InitAMDILLowering()
111 if (VT != MVT::i64 && VT != MVT::v2i64) { in InitAMDILLowering()
159 setOperationAction(ISD::MULHU, MVT::v2i64, Expand); in InitAMDILLowering()
161 setOperationAction(ISD::MULHS, MVT::v2i64, Expand); in InitAMDILLowering()
162 setOperationAction(ISD::ADD, MVT::v2i64, Expand); in InitAMDILLowering()
163 setOperationAction(ISD::SREM, MVT::v2i64, Expand); in InitAMDILLowering()
165 setOperationAction(ISD::SDIV, MVT::v2i64, Expand); in InitAMDILLowering()
166 setOperationAction(ISD::TRUNCATE, MVT::v2i64, Expand); in InitAMDILLowering()
167 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Expand); in InitAMDILLowering()
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/ARM/
DARMCallingConv.td28 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
47 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
61 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
73 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
89 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
139 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
149 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
167 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
179 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
DARMTargetTransformInfo.cpp216 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
217 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
454 { ISD::VECTOR_SHUFFLE, MVT::v2i64, 1 }, in getShuffleCost()
502 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
503 { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
504 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
505 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
539 if (LT.second == MVT::v2i64 && in getArithmeticInstrCost()
DARMInstrNEON.td3212 v2i32, v2i64, OpNode>;
3229 v2i32, v2i64, IntOp>;
3241 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3242 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3295 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
3297 v2i64, v2i64, OpNode, Commutable>;
3403 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3405 v2i64, v2i64, IntOp, Commutable>;
3417 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3419 v2i64, v2i64, IntOp>;
[all …]
DARMRegisterInfo.td302 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
310 def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
314 def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
327 def DPair : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
400 def DPairSpc : RegisterClass<"ARM", [v2i64], 64, (add Tuples2DSpc)>;
/freebsd-10-stable/contrib/llvm/patches/
Dpatch-r271597-clang-r217410-i386-garbage-float.diff32 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
37 // Custom lower v2i64 and v2f64 selects.
39 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/
DAArch64InstrNEON.td163 [(set (v2i64 VPR128:$Rd),
164 (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
397 def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
429 def : Pat<(v2i64 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
454 def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
486 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
487 (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
720 [(set (v2i64 VPR128:$Rd),
721 (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
746 v2i32, v4i32, v2i64, 0>;
[all …]
DAArch64RegisterInfo.td167 [f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
175 [f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
240 def DPair : RegisterClass<"AArch64", [v2i64], 64, (add Tuples2D)>;
/freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/
DValueTypes.h89 v2i64 = 38, // 2 x i64 enumerator
217 SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 || in is128BitVector()
292 case v2i64: in getVectorElementType()
346 case v2i64: in getVectorNumElements()
411 case v2i64: in getSizeInBits()
538 if (NumElements == 2) return MVT::v2i64; in getVectorVT()
DValueTypes.td61 def v2i64 : ValueType<128, 38>; // 2 x i64 vector value
/freebsd-10-stable/contrib/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td161 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
163 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
165 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
167 def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
169 def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
171 def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
173 def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
175 def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>;
177 def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
179 def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>;
[all …]
DMipsSEInstrInfo.cpp211 else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64)) in storeRegToStack()
252 else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64)) in loadRegFromStack()
DMipsSEISelLowering.cpp91 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass); in MipsSETargetLowering()
192 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) { in addMSAIntType()
1275 if (ResVecTy == MVT::v2i64) { in lowerMSASplatZExt()
1304 if (VecTy == MVT::v2i64) { in getBuildVectorSplat()
1342 if (VecTy == MVT::v2i64) { in lowerMSABinaryBitImmIntr()
1353 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, in lowerMSABinaryBitImmIntr()
1364 if (VecTy == MVT::v2i64) in lowerMSABinaryBitImmIntr()
/freebsd-10-stable/contrib/llvm/lib/Target/NVPTX/
DNVPTXVector.td73 // Extract v2i64
78 (v2i64 V2I64Regs:$src), imm:$c))],
161 // Insert v2i64
772 def : Pat<(v2i64 (vec_shuf:$op V2I64Regs:$src1, V2I64Regs:$src2)),
1325 // v2i64 -> v4i32
1332 // v4i32 -> v2i64
1333 def : Pat<(v2i64 (bitconvert V4I32Regs:$s)),
1398 // v2i64 -> v4f32
1409 // v2i64 -> v2f64
1442 // v2i64 <- v4f32
[all …]
/freebsd-10-stable/contrib/llvm/lib/IR/
DValueTypes.cpp156 case MVT::v2i64: return "v2i64"; in getEVTString()
224 case MVT::v2i64: return VectorType::get(Type::getInt64Ty(Context), 2); in getTypeForEVT()
/freebsd-10-stable/contrib/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp206 DecodeUNPCKHMask(MVT::v2i64, ShuffleMask); in EmitAnyX86InstComments()
279 DecodeUNPCKLMask(MVT::v2i64, ShuffleMask); in EmitAnyX86InstComments()
/freebsd-10-stable/contrib/llvm/utils/TableGen/
DCodeGenTarget.cpp97 case MVT::v2i64: return "MVT::v2i64"; in getEnumName()

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