Searched refs:post_div (Results 1 – 6 of 6) sorted by relevance
| /freebsd-10-stable/sys/dev/drm2/radeon/ |
| D | radeon_clocks.c | 43 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
58 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_get_engine_clock()
59 if (post_div == 2) in radeon_legacy_get_engine_clock()
61 else if (post_div == 3) in radeon_legacy_get_engine_clock()
63 else if (post_div == 4) in radeon_legacy_get_engine_clock()
73 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local
88 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; in radeon_legacy_get_memory_clock()
89 if (post_div == 2) in radeon_legacy_get_memory_clock()
91 else if (post_div == 3) in radeon_legacy_get_memory_clock()
93 else if (post_div == 4) in radeon_legacy_get_memory_clock()
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| D | radeon_display.c | 750 u32 post_div, in avivo_get_fb_div() argument
755 u32 tmp = post_div * ref_div; in avivo_get_fb_div()
770 u32 vco, post_div, tmp; in avivo_get_post_div() local
773 return pll->post_div; in avivo_get_post_div()
787 post_div = vco / target_clock; in avivo_get_post_div()
792 post_div++; in avivo_get_post_div()
795 post_div--; in avivo_get_post_div()
798 if (post_div > pll->max_post_div) in avivo_get_post_div()
799 post_div = pll->max_post_div; in avivo_get_post_div()
800 else if (post_div < pll->min_post_div) in avivo_get_post_div()
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| D | radeon_legacy_tv.c | 872 int post_div; in get_post_div() local
874 case 1: post_div = 0; break; in get_post_div()
875 case 2: post_div = 1; break; in get_post_div()
876 case 3: post_div = 4; break; in get_post_div()
877 case 4: post_div = 2; break; in get_post_div()
878 case 6: post_div = 6; break; in get_post_div()
879 case 8: post_div = 3; break; in get_post_div()
880 case 12: post_div = 7; break; in get_post_div()
882 default: post_div = 5; break; in get_post_div()
884 return post_div; in get_post_div()
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| D | radeon_legacy_crtc.c | 732 } *post_div, post_divs[] = { in radeon_set_pll() local
798 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_set_pll()
799 if (post_div->divider == post_divider) in radeon_set_pll()
803 if (!post_div->divider) in radeon_set_pll()
804 post_div = &post_divs[0]; in radeon_set_pll()
819 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); in radeon_set_pll()
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| D | atombios_crtc.c | 778 u32 post_div, in atombios_crtc_program_pll() argument
805 args.v1.ucPostDiv = post_div; in atombios_crtc_program_pll()
815 args.v2.ucPostDiv = post_div; in atombios_crtc_program_pll()
825 args.v3.ucPostDiv = post_div; in atombios_crtc_program_pll()
842 args.v5.ucPostDiv = post_div; in atombios_crtc_program_pll()
864 args.v6.ucPostDiv = post_div; in atombios_crtc_program_pll()
1000 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in atombios_crtc_set_pll() local
1021 pll->post_div = radeon_crtc->pll_post_div; in atombios_crtc_set_pll()
1026 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1029 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
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| D | radeon_mode.h | 160 uint32_t post_div; member
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