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Searched refs:msr (Results 1 – 25 of 111) sorted by relevance

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/freebsd-10-stable/sys/x86/cpufreq/
Dhwpstate.c79 #define AMD_10H_11H_GET_PSTATE_MAX_VAL(msr) (((msr) >> 4) & 0x7) argument
80 #define AMD_10H_11H_GET_PSTATE_LIMIT(msr) (((msr)) & 0x7) argument
82 #define AMD_10H_11H_CUR_VID(msr) (((msr) >> 9) & 0x7F) argument
83 #define AMD_10H_11H_CUR_DID(msr) (((msr) >> 6) & 0x07) argument
84 #define AMD_10H_11H_CUR_FID(msr) ((msr) & 0x3F) argument
86 #define AMD_17H_CUR_VID(msr) (((msr) >> 14) & 0xFF) argument
87 #define AMD_17H_CUR_DID(msr) (((msr) >> 8) & 0x3F) argument
88 #define AMD_17H_CUR_FID(msr) ((msr) & 0xFF) argument
168 uint64_t msr; in hwpstate_goto_pstate() local
172 msr = rdmsr(MSR_AMD_10H_11H_LIMIT); in hwpstate_goto_pstate()
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Dp4tcc.c263 uint64_t mask, msr; in p4tcc_set() local
284 msr = rdmsr(MSR_THERM_CONTROL); in p4tcc_set()
286 msr &= ~(mask | TCC_ENABLE_ONDEMAND); in p4tcc_set()
288 msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND; in p4tcc_set()
289 wrmsr(MSR_THERM_CONTROL, msr); in p4tcc_set()
298 if (msr & TCC_ENABLE_ONDEMAND) in p4tcc_set()
310 uint64_t msr; in p4tcc_get() local
326 msr = rdmsr(MSR_THERM_CONTROL); in p4tcc_get()
327 val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1); in p4tcc_get()
Dest.c908 static int est_table_info(device_t dev, uint64_t msr, freq_info **freqs);
909 static int est_msr_info(device_t dev, uint64_t msr, freq_info **freqs);
991 uint64_t msr; in est_probe() local
1009 msr = rdmsr(MSR_MISC_ENABLE); in est_probe()
1010 if ((msr & MSR_SS_ENABLE) == 0) { in est_probe()
1011 wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE); in est_probe()
1016 msr = rdmsr(MSR_MISC_ENABLE); in est_probe()
1017 if ((msr & MSR_SS_ENABLE) == 0) { in est_probe()
1073 uint64_t msr; in est_get_info() local
1077 msr = rdmsr(MSR_PERF_STATUS); in est_get_info()
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/freebsd-10-stable/sys/dev/coretemp/
Dcoretemp.c154 uint64_t msr; in coretemp_attach() local
187 msr = rdmsr(MSR_BIOS_SIGN); in coretemp_attach()
188 msr = msr >> 32; in coretemp_attach()
189 if (msr < 0x39) { in coretemp_attach()
210 msr = rdmsr(MSR_IA32_EXT_CONFIG); in coretemp_attach()
211 if (msr & (1 << 30)) in coretemp_attach()
237 ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr); in coretemp_attach()
239 tjtarget = (msr >> 16) & 0xff; in coretemp_attach()
309 uint64_t msr; in coretemp_get_thermal_msr() local
325 msr = rdmsr(MSR_THERM_STATUS); in coretemp_get_thermal_msr()
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/freebsd-10-stable/usr.sbin/bhyve/
Duart_emul.c105 uint8_t msr; /* Modem status register (R/W) */ member
278 uint8_t msr; in modem_status() local
285 msr = 0; in modem_status()
287 msr |= MSR_CTS; in modem_status()
289 msr |= MSR_DSR; in modem_status()
291 msr |= MSR_RI; in modem_status()
293 msr |= MSR_DCD; in modem_status()
299 msr = MSR_DCD | MSR_DSR; in modem_status()
301 assert((msr & MSR_DELTA_MASK) == 0); in modem_status()
303 return (msr); in modem_status()
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/freebsd-10-stable/sys/amd64/amd64/
Dinitcpu.c92 uint64_t msr; in init_amd() local
123 msr = rdmsr(MSR_NB_CFG1); in init_amd()
124 msr |= (uint64_t)1 << 54; in init_amd()
125 wrmsr(MSR_NB_CFG1, msr); in init_amd()
137 msr = rdmsr(0xc001102a); in init_amd()
138 msr &= ~((uint64_t)1 << 24); in init_amd()
139 wrmsr(0xc001102a, msr); in init_amd()
151 msr = rdmsr(0xc0011020); in init_amd()
152 msr |= (uint64_t)1 << 15; in init_amd()
153 wrmsr(0xc0011020, msr); in init_amd()
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Damd64_mem.c177 int i, j, msr; in amd64_mrfetch() local
183 msr = MSR_MTRR64kBase; in amd64_mrfetch()
184 for (i = 0; i < (MTRR_N64K / 8); i++, msr++) { in amd64_mrfetch()
185 msrv = rdmsr(msr); in amd64_mrfetch()
195 msr = MSR_MTRR16kBase; in amd64_mrfetch()
196 for (i = 0; i < (MTRR_N16K / 8); i++, msr++) { in amd64_mrfetch()
197 msrv = rdmsr(msr); in amd64_mrfetch()
207 msr = MSR_MTRR4kBase; in amd64_mrfetch()
208 for (i = 0; i < (MTRR_N4K / 8); i++, msr++) { in amd64_mrfetch()
209 msrv = rdmsr(msr); in amd64_mrfetch()
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/freebsd-10-stable/sys/i386/i386/
Di686_mem.c171 int i, j, msr; in i686_mrfetch() local
177 msr = MSR_MTRR64kBase; in i686_mrfetch()
178 for (i = 0; i < (MTRR_N64K / 8); i++, msr++) { in i686_mrfetch()
179 msrv = rdmsr(msr); in i686_mrfetch()
189 msr = MSR_MTRR16kBase; in i686_mrfetch()
190 for (i = 0; i < (MTRR_N16K / 8); i++, msr++) { in i686_mrfetch()
191 msrv = rdmsr(msr); in i686_mrfetch()
201 msr = MSR_MTRR4kBase; in i686_mrfetch()
202 for (i = 0; i < (MTRR_N4K / 8); i++, msr++) { in i686_mrfetch()
203 msrv = rdmsr(msr); in i686_mrfetch()
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Dinitcpu.c801 uint64_t msr; in initializecpu() local
803 msr = rdmsr(MSR_EFER) | EFER_NXE; in initializecpu()
804 wrmsr(MSR_EFER, msr); in initializecpu()
897 u_int64_t msr; in enable_K5_wt_alloc() local
906 msr = rdmsr(0x83); /* HWCR */ in enable_K5_wt_alloc()
907 wrmsr(0x83, msr & !(0x10)); in enable_K5_wt_alloc()
915 msr = Maxmem / 16; in enable_K5_wt_alloc()
917 msr = 0; in enable_K5_wt_alloc()
918 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE; in enable_K5_wt_alloc()
922 msr |= AMD_WT_ALLOC_PRE; in enable_K5_wt_alloc()
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/freebsd-10-stable/sys/amd64/vmm/
Dvmm_lapic.c140 x2apic_msr(u_int msr) in x2apic_msr() argument
142 if (msr >= 0x800 && msr <= 0xBFF) in x2apic_msr()
149 x2apic_msr_to_regoff(u_int msr) in x2apic_msr_to_regoff() argument
152 return ((msr - 0x800) << 4); in x2apic_msr_to_regoff()
156 lapic_msr(u_int msr) in lapic_msr() argument
159 if (x2apic_msr(msr) || (msr == MSR_APICBASE)) in lapic_msr()
166 lapic_rdmsr(struct vm *vm, int cpu, u_int msr, uint64_t *rval, bool *retu) in lapic_rdmsr() argument
174 if (msr == MSR_APICBASE) { in lapic_rdmsr()
178 offset = x2apic_msr_to_regoff(msr); in lapic_rdmsr()
186 lapic_wrmsr(struct vm *vm, int cpu, u_int msr, uint64_t val, bool *retu) in lapic_wrmsr() argument
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/freebsd-10-stable/sys/powerpc/powerpc/
Daltivec.c49 int msr; in enable_vec() local
79 msr = mfmsr(); in enable_vec()
80 mtmsr(msr | PSL_VEC); in enable_vec()
104 mtmsr(msr); in enable_vec()
110 int msr; in save_vec() local
118 msr = mfmsr(); in save_vec()
119 mtmsr(msr | PSL_VEC); in save_vec()
143 mtmsr(msr); in save_vec()
Dfpu.c49 int msr; in enable_fpu() local
80 msr = mfmsr(); in enable_fpu()
81 mtmsr(msr | PSL_FP); in enable_fpu()
105 mtmsr(msr); in enable_fpu()
111 int msr; in save_fpu() local
119 msr = mfmsr(); in save_fpu()
120 mtmsr(msr | PSL_FP); in save_fpu()
143 mtmsr(msr); in save_fpu()
Dcpu.c277 register_t msr; in cpu_est_clockrate() local
283 msr = mfmsr(); in cpu_est_clockrate()
284 mtmsr(msr & ~PSL_EE); in cpu_est_clockrate()
303 mtmsr(msr); in cpu_est_clockrate()
322 mtmsr(msr); in cpu_est_clockrate()
613 register_t msr; in cpu_idle_60x() local
619 msr = mfmsr(); in cpu_idle_60x()
634 :: "r"(msr | PSL_POW)); in cpu_idle_60x()
638 mtmsr(msr | PSL_POW); in cpu_idle_60x()
648 register_t msr; in cpu_idle_booke() local
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/freebsd-10-stable/sys/powerpc/cpufreq/
Dpcr.c110 register_t msr; in write_scom() local
115 msr = mfmsr(); in write_scom()
116 mtmsr(msr & ~PSL_EE); isync(); in write_scom()
129 mtmsr(msr); isync(); in write_scom()
135 register_t msr; in read_scom() local
138 msr = mfmsr(); in read_scom()
139 mtmsr(msr & ~PSL_EE); isync(); in read_scom()
149 mtmsr(msr); isync(); in read_scom()
263 register_t pcr, msr; in pcr_set() local
281 msr = mfmsr(); in pcr_set()
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/freebsd-10-stable/sys/powerpc/aim/
Dmoea64_native.c132 register_t msr; in TLBIE() local
167 : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1) in TLBIE()
176 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) argument
177 #define ENABLE_TRANS(msr) mtmsr(msr) argument
372 register_t msr; in moea64_bootstrap_native() local
392 DISABLE_TRANS(msr); in moea64_bootstrap_native()
394 ENABLE_TRANS(msr); in moea64_bootstrap_native()
406 DISABLE_TRANS(msr); in moea64_bootstrap_native()
409 ENABLE_TRANS(msr); in moea64_bootstrap_native()
421 register_t msr, scratch; in tlbia() local
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Dmachdep.c262 register_t msr, scratch; in powerpc_init() local
399 msr = mfmsr(); in powerpc_init()
400 mtmsr((msr & ~(PSL_IR | PSL_DR)) | PSL_RI); in powerpc_init()
534 mtmsr(msr); in powerpc_init()
721 register_t msr; in spinlock_enter() local
725 msr = intr_disable(); in spinlock_enter()
727 td->td_md.md_saved_msr = msr; in spinlock_enter()
737 register_t msr; in spinlock_exit() local
741 msr = td->td_md.md_saved_msr; in spinlock_exit()
744 intr_restore(msr); in spinlock_exit()
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/freebsd-10-stable/sys/amd64/vmm/intel/
Dvmx_msr.h62 int msr_bitmap_change_access(char *bitmap, u_int msr, int access);
64 #define guest_msr_rw(vmx, msr) \ argument
65 msr_bitmap_change_access((vmx)->msr_bitmap, (msr), MSR_BITMAP_ACCESS_RW)
67 #define guest_msr_ro(vmx, msr) \ argument
68 msr_bitmap_change_access((vmx)->msr_bitmap, (msr), MSR_BITMAP_ACCESS_READ)
Dvmx_msr.c152 msr_bitmap_change_access(char *bitmap, u_int msr, int access) in msr_bitmap_change_access() argument
156 if (msr <= 0x00001FFF) in msr_bitmap_change_access()
157 byte = msr / 8; in msr_bitmap_change_access()
158 else if (msr >= 0xC0000000 && msr <= 0xC0001FFF) in msr_bitmap_change_access()
159 byte = 1024 + (msr - 0xC0000000) / 8; in msr_bitmap_change_access()
163 bit = msr & 0x7; in msr_bitmap_change_access()
/freebsd-10-stable/sys/arm/arm/
Dcpufunc_asm_sheeva.S47 msr cpsr_c, r3
58 msr cpsr_c, r2
92 msr cpsr_c, r3
96 msr cpsr_c, lr
135 msr cpsr_c, r3
139 msr cpsr_c, lr
187 msr cpsr_c, r3
191 msr cpsr_c, lr
230 msr cpsr_c, r3
234 msr cpsr_c, lr
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Dexception.S110 msr spsr_fsxc, r0; \
119 msr spsr_fsxc, r0; \
147 msr cpsr_c, r2; /* Punch into SVC mode */ \
154 msr spsr_fsxc, r3; /* Restore correct spsr */ \
184 msr cpsr_c, r2; /* Punch into SVC mode */ \
191 msr spsr_fsxc, r3; /* Restore correct spsr */ \
212 msr spsr_fsxc, r0; /* restore SPSR */ \
220 msr spsr_fsxc, r0; /* restore SPSR */ \
248 msr cpsr_c, r1; /* Disable interrupts */ \
258 msr cpsr_c, r4; /* Restore interrupts */ \
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Dsetstack.s67 msr cpsr_fsxc, r2
71 msr cpsr_fsxc, r3 /* Restore the old mode */
86 msr cpsr_fsxc, r2
90 msr cpsr_fsxc, r3 /* Restore the old mode */
/freebsd-10-stable/sys/powerpc/include/
Dcpufunc.h189 register_t msr; in intr_disable() local
191 msr = mfmsr(); in intr_disable()
192 mtmsr(msr & ~PSL_EE); in intr_disable()
193 return (msr); in intr_disable()
197 intr_restore(register_t msr) in intr_restore() argument
200 mtmsr(msr); in intr_restore()
/freebsd-10-stable/sys/x86/x86/
Didentcpu.c1322 uint64_t msr; in fix_cpuid() local
1335 msr = rdmsr(MSR_IA32_MISC_ENABLE); in fix_cpuid()
1336 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) { in fix_cpuid()
1337 msr &= ~IA32_MISC_EN_LIMCPUID; in fix_cpuid()
1338 wrmsr(MSR_IA32_MISC_ENABLE, msr); in fix_cpuid()
1352 msr = rdmsr(MSR_EXTFEATURES); in fix_cpuid()
1353 if ((msr & ((uint64_t)1 << 54)) == 0) { in fix_cpuid()
1354 msr |= (uint64_t)1 << 54; in fix_cpuid()
1355 wrmsr(MSR_EXTFEATURES, msr); in fix_cpuid()
2096 uint64_t msr; in print_svm_info() local
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/freebsd-10-stable/sys/dev/usb/net/
Druephy.c196 int bmsr, bmcr, msr; in ruephy_status() local
201 msr = PHY_READ(phy, RUEPHY_MII_MSR) | PHY_READ(phy, RUEPHY_MII_MSR); in ruephy_status()
202 if (msr & RUEPHY_MSR_LINK) in ruephy_status()
220 if (msr & RUEPHY_MSR_SPEED100) in ruephy_status()
225 if (msr & RUEPHY_MSR_DUPLEX) in ruephy_status()
/freebsd-10-stable/lib/libc/arm/aeabi/
Daeabi_asm_double.S59 msr cpsr_c, #(0)
73 msr cpsr_c, #(PCR_Z | PCR_C)
78 msr cpsr_c, #(PCR_C)
115 msr cpsr_c, #(PCR_C)

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