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Searched refs:memw (Results 1 – 5 of 5) sorted by relevance

/freebsd-10-stable/sys/x86/iommu/
Dintel_qi.c159 bool memw, bool fence) in dmar_qi_emit_wait_descr() argument
165 (memw ? DMAR_IQ_DESCR_WAIT_SW : 0) | in dmar_qi_emit_wait_descr()
167 (memw ? DMAR_IQ_DESCR_WAIT_SD(seq) : 0), in dmar_qi_emit_wait_descr()
168 memw ? unit->inv_waitd_seq_hw_phys : 0); in dmar_qi_emit_wait_descr()
/freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV4.td228 def LDriw_abs_set_V4 : T_LD_abs_set <"memw", IntRegs>;
281 defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel;
482 def STriw_abs_set_V4 : T_ST_abs_set <"memw", IntRegs>;
575 defm STriw_indexed_shl: ST_Idxd_shl<"memw", "STriw", IntRegs>,
576 ST_Idxd_shl_nv<"memw", "STriw", IntRegs>, AddrModeRel;
637 defm STriw_shl : ST_LongOff <"memw", "STriw", store>, NewValueRel;
721 defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel, PredNewRel;
781 // memw(Re=#U6)=Rt
797 // memw(Rx++#s4:2)=Rt
798 // memw(Rx++#s4:2:circ(Mu))=Rt
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DHexagonInstrInfoV5.td84 (ins MEMri:$addr), "$dst = memw($addr)",
92 "$dst = memw($src1+#$offset)",
100 "memw($addr) = $src1",
107 "memw($src1+#$src2) = $src3",
DHexagonInstrInfo.td952 defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
1031 defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
1111 defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,
1433 defm POST_STwri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
1504 defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
1578 defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext,
1953 // this pattern to use memw(#foo).
2316 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
2321 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2326 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
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DHexagonInstrFormats.td66 def WordAccess : MemAccessSize<3>;// Word access instruction (memw).