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Searched refs:gpu_offset (Results 1 – 11 of 11) sorted by relevance

/freebsd-10-stable/sys/dev/drm2/radeon/
Devergreen_cs.c1364 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1436 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1448 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1460 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1472 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1496 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1516 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1719 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1736 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1777 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
[all …]
Dr600_cs.c929 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32; in r600_cs_packet_next_reloc_nomm()
930 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0]; in r600_cs_packet_next_reloc_nomm()
1217 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1219 track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset; in r600_cs_check_reg()
1238 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1347 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1378 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1414 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1417 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset; in r600_cs_check_reg()
1428 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
[all …]
Dr200.c192 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()
205 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()
229 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()
231 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()
275 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()
369 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r200_packet0_check()
Dr300.c646 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r300_packet0_check()
659 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r300_packet0_check()
688 ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset); in r300_packet0_check()
697 tmp = idx_value + ((u32)reloc->lobj.gpu_offset); in r300_packet0_check()
1058 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r300_packet0_check()
1103 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r300_packet0_check()
1168 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); in r300_packet3_check()
Dr100.c1268 tmp += (((u32)reloc->lobj.gpu_offset) >> 10); in r100_reloc_pitch_offset()
1319 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); in r100_packet3_load_vbpntr()
1331 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); in r100_packet3_load_vbpntr()
1345 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); in r100_packet3_load_vbpntr()
1697 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r100_packet0_check()
1710 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r100_packet0_check()
1731 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); in r100_packet0_check()
1733 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r100_packet0_check()
1751 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r100_packet0_check()
1769 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); in r100_packet0_check()
[all …]
Dradeon_ttm.c140 man->gpu_offset = rdev->mc.gtt_start; in radeon_init_mem_type()
162 man->gpu_offset = rdev->mc.vram_start; in radeon_init_mem_type()
Dradeon_object.c391 lobj->gpu_offset = radeon_bo_gpu_offset(bo); in radeon_bo_list_validate()
Dradeon.h363 uint64_t gpu_offset; member
/freebsd-10-stable/sys/dev/drm2/i915/
Di915_gem.c1073 const char *gpu_vaddr, int gpu_offset, in __copy_to_user_swizzled() argument
1079 int cacheline_end = roundup2(gpu_offset + 1, 64); in __copy_to_user_swizzled()
1080 int this_length = min(cacheline_end - gpu_offset, length); in __copy_to_user_swizzled()
1081 int swizzled_gpu_offset = gpu_offset ^ 64; in __copy_to_user_swizzled()
1090 gpu_offset += this_length; in __copy_to_user_swizzled()
1098 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, in __copy_from_user_swizzled() argument
1105 int cacheline_end = roundup2(gpu_offset + 1, 64); in __copy_from_user_swizzled()
1106 int this_length = min(cacheline_end - gpu_offset, length); in __copy_from_user_swizzled()
1107 int swizzled_gpu_offset = gpu_offset ^ 64; in __copy_from_user_swizzled()
1116 gpu_offset += this_length; in __copy_from_user_swizzled()
/freebsd-10-stable/sys/dev/drm2/ttm/
Dttm_bo_driver.h275 unsigned long gpu_offset; member
Dttm_bo.c69 printf(" gpu_offset: 0x%08lX\n", man->gpu_offset); in ttm_mem_type_debug()
499 bdev->man[bo->mem.mem_type].gpu_offset; in ttm_bo_handle_move_mem()