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Searched refs:getLocVT (Results 1 – 16 of 16) sorted by relevance

/freebsd-10-stable/contrib/llvm/patches/
Dpatch-r262261-llvm-r198145-sparc.diff81 + MVT ValTy = VA.getLocVT();
84 - if (!VA.isRegLoc() || VA.getLocVT() != MVT::f64)
120 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
123 - Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
127 + || VA.getLocVT() != MVT::i128)
128 + Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
134 + && VA.getLocVT() == MVT::i128) {
/freebsd-10-stable/contrib/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp214 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
276 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
279 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
282 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
307 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
374 assert(VA.getLocVT() == MVT::f64); in LowerFormalArguments_32()
404 if (VA.getLocVT() == MVT::f32) in LowerFormalArguments_32()
406 else if (VA.getLocVT() != MVT::i32) { in LowerFormalArguments_32()
408 DAG.getValueType(VA.getLocVT())); in LowerFormalArguments_32()
409 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); in LowerFormalArguments_32()
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/X86/
DX86FastISel.cpp2058 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in DoSelectCall()
2060 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), in DoSelectCall()
2063 ArgVT = VA.getLocVT(); in DoSelectCall()
2067 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in DoSelectCall()
2069 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), in DoSelectCall()
2072 ArgVT = VA.getLocVT(); in DoSelectCall()
2076 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in DoSelectCall()
2078 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), in DoSelectCall()
2081 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), in DoSelectCall()
2084 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), in DoSelectCall()
[all …]
DX86ISelLowering.cpp1827 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
1829 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
1831 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
1833 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
1880 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2135 ValVT = VA.getLocVT(); in LowerMemArgument()
2207 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
2593 EVT RegVT = VA.getLocVT(); in LowerCall()
2731 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; in LowerCall()
/freebsd-10-stable/contrib/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp457 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
500 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; in LowerCCCArguments()
503 << EVT(VA.getLocVT()).getEVTString() in LowerCCCArguments()
512 InVal = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
559 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
615 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
618 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
621 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
/freebsd-10-stable/contrib/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp949 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
952 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
955 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1136 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
1156 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; in LowerCCCArguments()
1159 << EVT(VA.getLocVT()).getEVTString() in LowerCCCArguments()
1170 ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
1305 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp340 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
483 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
486 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
489 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
868 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
894 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3; in LowerFormalArguments()
911 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerFormalArguments()
/freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp600 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
603 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
623 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
625 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
627 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
658 EVT LocVT = VA.getLocVT(); in LowerFormalArguments()
699 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32) in LowerFormalArguments()
834 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32) in LowerCall()
914 VA.getLocVT(), Glue); in LowerCall()
961 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT())); in LowerReturn()
/freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/
DCallingConvLower.h124 MVT getLocVT() const { return LocVT; } in getLocVT() function
/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp1169 MVT RegVT = VA.getLocVT(); in LowerFormalArguments()
1177 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8, in LowerFormalArguments()
1181 ArgValue = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerFormalArguments()
1296 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerReturn()
1299 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerReturn()
1305 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
1424 VA.getLocVT(), in LowerCall()
1425 DAG.getUNDEF(VA.getLocVT()), in LowerCall()
1433 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
1451 VA.getLocVT().getSizeInBits(); in LowerCall()
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/ARM/
DARMFastISel.cpp1984 if (VA.getLocVT() != MVT::f64 || in ProcessCallArgs()
2033 MVT DestVT = VA.getLocVT(); in ProcessCallArgs()
2042 MVT DestVT = VA.getLocVT(); in ProcessCallArgs()
2049 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg, in ProcessCallArgs()
2053 ArgVT = VA.getLocVT(); in ProcessCallArgs()
2067 assert(VA.getLocVT() == MVT::f64 && in ProcessCallArgs()
DARMISelLowering.cpp1333 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 && in LowerCallResult()
1353 if (VA.getLocVT() == MVT::v2f64) { in LowerCallResult()
1371 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), in LowerCallResult()
1510 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1513 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1516 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1519 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
1525 if (VA.getLocVT() == MVT::v2f64) { in LowerCall()
1550 assert(VA.getLocVT() == MVT::i32 && in LowerCall()
2069 EVT RegVT = VA.getLocVT(); in IsEligibleForTailCallOptimization()
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/Mips/
DMipsISelLowering.cpp2369 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); in LowerCall()
2531 RVLocs[i].getLocVT(), InFlag); in LowerCallResult()
2535 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) in LowerCallResult()
2602 MVT RegVT = VA.getLocVT(); in LowerFormalArguments()
2734 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) in LowerReturn()
2735 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val); in LowerReturn()
2741 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp1243 MVT DestVT = VA.getLocVT(); in processCallArgs()
1255 MVT DestVT = VA.getLocVT(); in processCallArgs()
1553 MVT DestVT = VA.getLocVT(); in SelectRet()
DPPCISelLowering.cpp2049 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; in LowerFormalArguments_32SVR4()
3390 VA.getLocReg(), VA.getLocVT(), InFlag); in LowerCallResult()
3401 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val, in LowerCallResult()
3406 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val, in LowerCallResult()
3708 seenFloatArg |= VA.getLocVT().isFloatingPoint(); in LowerCall_32SVR4()
4552 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerReturn()
4555 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerReturn()
4558 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerReturn()
4564 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd-10-stable/contrib/llvm/lib/Target/R600/
DSIISelLowering.cpp276 EVT VT = VA.getLocVT(); in LowerFormalArguments()