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Searched refs:getLocReg (Results 1 – 17 of 17) sorted by relevance

/freebsd-10-stable/contrib/llvm/patches/
Dpatch-r262261-llvm-r198145-sparc.diff93 - unsigned Offset = 8 * (VA.getLocReg() - SP::D0);
96 + unsigned Offset = argSize * (VA.getLocReg() - firstReg);
136 + unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
157 + RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()),
159 + RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1),
/freebsd-10-stable/contrib/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp209 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), in LowerReturn_32()
214 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
295 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
303 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn_64()
307 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
376 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments_32()
391 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments_32()
402 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments_32()
564 unsigned VReg = MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_64()
818 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi)); in LowerCall_32()
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/ARM/
DARMFastISel.cpp2062 VA.getLocReg()) in ProcessCallArgs()
2064 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
2076 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
2077 .addReg(NextVA.getLocReg(), RegState::Define) in ProcessCallArgs()
2079 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
2080 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
2121 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2122 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2124 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2125 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
[all …]
DARMISelLowering.cpp1342 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1347 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1359 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1363 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1371 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), in LowerCallResult()
1416 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); in PassF64ArgInRegs()
1419 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1))); in PassF64ArgInRegs()
1556 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
2030 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) in IsEligibleForTailCallOptimization()
2192 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag); in LowerReturn()
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/X86/
DX86FastISel.cpp833 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) in X86SelectRet()
862 unsigned DstReg = VA.getLocReg(); in X86SelectRet()
871 RetRegs.push_back(VA.getLocReg()); in X86SelectRet()
2111 VA.getLocReg()).addReg(Arg); in DoSelectCall()
2112 RegArgs.push_back(VA.getLocReg()); in DoSelectCall()
2268 if ((RVLocs[i].getLocReg() == X86::ST0 || in DoSelectCall()
2269 RVLocs[i].getLocReg() == X86::ST1)) { in DoSelectCall()
2278 CopyReg).addReg(RVLocs[i].getLocReg()); in DoSelectCall()
2279 UsedRegs.push_back(RVLocs[i].getLocReg()); in DoSelectCall()
DX86ISelLowering.cpp1838 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && in LowerReturn()
1851 if (VA.getLocReg() == X86::ST0 || in LowerReturn()
1852 VA.getLocReg() == X86::ST1) { in LowerReturn()
1866 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { in LowerReturn()
1878 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); in LowerReturn()
1880 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
1998 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { in LowerCallResult()
2014 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), in LowerCallResult()
2232 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
2633 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp469 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
553 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
559 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
628 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
733 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
/freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp336 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
340 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
382 RVLocs[i].getLocReg(), in LowerCallResult()
516 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
873 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
878 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
/freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/
DCallingConvLower.h122 unsigned getLocReg() const { assert(isRegLoc()); return Loc; } in getLocReg() function
/freebsd-10-stable/contrib/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp962 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
1051 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
1148 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
1299 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
1305 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp1317 unsigned SourcePhysReg = VA.getLocReg(); in finishCall()
1530 unsigned RetReg = ValLocs[0].getLocReg(); in SelectRet()
1546 RetRegs.push_back(VA.getLocReg()); in SelectRet()
DPPCISelLowering.cpp2041 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4()
3390 VA.getLocReg(), VA.getLocVT(), InFlag); in LowerCallResult()
3710 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32SVR4()
4562 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); in LowerReturn()
4564 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp1171 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
1303 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); in LowerReturn()
1305 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
1441 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
1601 SDValue Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), in LowerCallResult()
1710 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) in IsEligibleForTailCallOptimization()
/freebsd-10-stable/contrib/llvm/lib/Target/Mips/
DMipsISelLowering.cpp2401 unsigned LocRegLo = VA.getLocReg(); in LowerCall()
2423 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
2530 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), in LowerCallResult()
2603 unsigned ArgReg = VA.getLocReg(); in LowerFormalArguments()
2737 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); in LowerReturn()
2741 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp685 MRI.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
763 unsigned Reg = VA.getLocReg(); in canUseSiblingCall()
825 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); in LowerCall()
913 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), in LowerCall()
958 unsigned Reg = VA.getLocReg(); in LowerReturn()
/freebsd-10-stable/contrib/llvm/lib/Target/R600/
DSIISelLowering.cpp290 unsigned Reg = VA.getLocReg(); in LowerFormalArguments()
315 Reg = ArgLocs[ArgIdx++].getLocReg(); in LowerFormalArguments()
DR600ISelLowering.cpp1364 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass); in LowerFormalArguments()