Searched refs:_MASKED_BIT_ENABLE (Results 1 – 6 of 6) sorted by relevance
429 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); in init_render_ring()433 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); in init_render_ring()461 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); in init_render_ring()
273 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); in i915_gem_load()403 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); in i915_gem_init_swizzling()405 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); in i915_gem_init_swizzling()447 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in i915_gem_init_ppgtt()456 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in i915_gem_init_ppgtt()
622 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1)); in __gen6_gt_force_wake_mt_get()
3395 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); in ivybridge_init_clock_gating()3442 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); in valleyview_init_clock_gating()3496 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); in gen3_init_clock_gating()
1055 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); in i915_disable_vblank()
35 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) macro