1 /*- 2 * Copyright (c) 2002 Jason L. Wright (jason@thought.net) 3 * Copyright (c) 2005 by Marius Strobl <marius@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULLAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * from: OpenBSD: schizoreg.h,v 1.8 2005/05/19 18:28:59 mickey Exp 28 * $FreeBSD: stable/10/sys/sparc64/pci/schizoreg.h 292789 2015-12-27 19:37:47Z marius $ 29 */ 30 31 #ifndef _SPARC64_PCI_SCHIZOREG_H_ 32 #define _SPARC64_PCI_SCHIZOREG_H_ 33 34 #define STX_NINTR 5 /* 4 via OFW + 1 CDMA */ 35 #define SCZ_NREG 3 36 #define TOM_NREG 4 37 38 #define STX_PCI 0 39 #define STX_CTRL 1 40 #define STX_PCICFG 2 41 #define STX_ICON 3 42 43 /* PCI configuration and status registers */ 44 #define SX_PCI_CFG_ICD 0x00110 45 #define STX_PCI_IOMMU 0x00200 46 #define STX_PCI_IOMMU_CTXFLUSH 0x00218 47 #define STX_PCI_IMAP_BASE 0x01000 48 #define STX_PCI_ICLR_BASE 0x01400 49 #define STX_PCI_INTR_RETRY_TIM 0x01a00 50 #define SCZ_PCI_DMA_SYNC 0x01a08 51 #define TOM_PCI_DMA_SYNC_COMP 0x01a10 52 #define TOMXMS_PCI_DMA_SYNC_PEND 0x01a18 53 #define STX_PCI_CTRL 0x02000 54 #define STX_PCI_AFSR 0x02010 55 #define STX_PCI_AFAR 0x02018 56 #define STX_PCI_DIAG 0x02020 57 #define XMS_PCI_PARITY_DETECT 0x02040 58 #define TOM_PCI_IOC_CSR 0x02248 59 #define TOM_PCI_IOC_TAG 0x02290 60 #define TOM_PCI_IOC_DATA 0x02290 61 #define XMS_PCI_X_ERR_STAT 0x02300 62 #define XMS_PCI_X_DIAG 0x02308 63 #define XMS_PCI_UPPER_RETRY_COUNTER 0x02310 64 #define STX_PCI_STRBUF 0x02800 65 #define STX_PCI_STRBUF_CTXFLUSH 0x02818 66 #define STX_PCI_IOMMU_SVADIAG 0x0a400 67 #define STX_PCI_IOMMU_TLB_CMP_DIAG 0x0a408 68 #define STX_PCI_IOMMU_QUEUE_DIAG 0x0a500 69 #define STX_PCI_IOMMU_TLB_TAG_DIAG 0x0a580 70 #define STX_PCI_IOMMU_TLB_DATA_DIAG 0x0a600 71 #define STX_PCI_IOBIO_DIAG 0x0a808 72 #define STX_PCI_STRBUF_CTXMATCH 0x10000 73 74 /* PCI configuration/idle check diagnostic register */ 75 #define SX_PCI_CFG_ICD_PCI_2_0_COMPAT 0x0000000000008000ULL 76 #define SX_PCI_CFG_ICD_DMAW_PERR_IEN 0x0000000000004000ULL 77 #define SX_PCI_CFG_ICD_IFC_NOT_IDLE 0x0000000000000010ULL 78 #define SX_PCI_CFG_ICD_MDU_NOT_IDLE 0x0000000000000008ULL 79 #define SX_PCI_CFG_ICD_MMU_NOT_IDLE 0x0000000000000004ULL 80 #define SX_PCI_CFG_ICD_PBM_NOT_IDLE 0x0000000000000002ULL 81 #define SX_PCI_CFG_ICD_STC_NOT_IDLE 0x0000000000000001ULL 82 83 /* PCI IOMMU control register */ 84 #define TOM_PCI_IOMMU_ERR_BAD_VA 0x0000000010000000ULL 85 #define TOM_PCI_IOMMU_ERR_ILLTSBTBW 0x0000000008000000ULL 86 #define TOM_PCI_IOMMU_ECC_ERR 0x0000000006000000ULL 87 #define TOM_PCI_IOMMU_TIMEOUT_ERR 0x0000000004000000ULL 88 #define TOM_PCI_IOMMU_INVALID_ERR 0x0000000002000000ULL 89 #define TOM_PCI_IOMMU_PROTECTION_ERR 0x0000000000000000ULL 90 #define TOM_PCI_IOMMU_ERRMASK \ 91 (TOM_PCI_IOMMU_PROTECTION_ERR | TOM_PCI_IOMMU_INVALID_ERR | \ 92 TOM_PCI_IOMMU_TIMEOUT_ERR | TOM_PCI_IOMMU_ECC_ERR) 93 #define TOM_PCI_IOMMU_ERR 0x0000000001000000ULL 94 95 /* PCI control/status register */ 96 #define SCZ_PCI_CTRL_BUS_UNUS 0x8000000000000000ULL 97 #define TOM_PCI_CTRL_DTO_ERR 0x4000000000000000ULL 98 #define TOM_PCI_CTRL_DTO_IEN 0x2000000000000000ULL 99 #define SCZ_PCI_CTRL_ESLCK 0x0008000000000000ULL 100 #define XMS_PCI_CTRL_DMA_WR_PERR 0x0008000000000000ULL 101 #define SCZ_PCI_CTRL_ERRSLOT 0x0007000000000000ULL 102 #define STX_PCI_CTRL_TTO_ERR 0x0000004000000000ULL 103 #define STX_PCI_CTRL_RTRY_ERR 0x0000002000000000ULL 104 #define STX_PCI_CTRL_MMU_ERR 0x0000001000000000ULL 105 #define SCZ_PCI_CTRL_SBH_ERR 0x0000000800000000ULL 106 #define STX_PCI_CTRL_SERR 0x0000000400000000ULL 107 #define SCZ_PCI_CTRL_PCISPD 0x0000000200000000ULL 108 #define XMS_PCI_CTRL_X_MODE 0x0000000100000000ULL 109 #define TOM_PCI_CTRL_PRM 0x0000000040000000ULL 110 #define TOM_PCI_CTRL_PRO 0x0000000020000000ULL 111 #define TOM_PCI_CTRL_PRL 0x0000000010000000ULL 112 #define STX_PCI_CTRL_PTO 0x0000000003000000ULL 113 #define XMS_PCI_CTRL_X_ERRINT_EN 0x0000000000100000ULL 114 #define STX_PCI_CTRL_MMU_IEN 0x0000000000080000ULL 115 #define STX_PCI_CTRL_SBH_IEN 0x0000000000040000ULL 116 #define STX_PCI_CTRL_ERR_IEN 0x0000000000020000ULL 117 #define STX_PCI_CTRL_ARB_PARK 0x0000000000010000ULL 118 #define SCZ_PCI_CTRL_PCIRST 0x0000000000000100ULL 119 #define STX_PCI_CTRL_ARB_MASK 0x00000000000000ffULL 120 #define XMS_PCI_CTRL_XMITS10_ARB_MASK 0x000000000000000fULL 121 122 /* PCI asynchronous fault status register */ 123 #define STX_PCI_AFSR_P_MA 0x8000000000000000ULL 124 #define STX_PCI_AFSR_P_TA 0x4000000000000000ULL 125 #define STX_PCI_AFSR_P_RTRY 0x2000000000000000ULL 126 #define STX_PCI_AFSR_P_PERR 0x1000000000000000ULL 127 #define STX_PCI_AFSR_P_TTO 0x0800000000000000ULL 128 #define STX_PCI_AFSR_P_UNUS 0x0400000000000000ULL 129 #define STX_PCI_AFSR_S_MA 0x0200000000000000ULL 130 #define STX_PCI_AFSR_S_TA 0x0100000000000000ULL 131 #define STX_PCI_AFSR_S_RTRY 0x0080000000000000ULL 132 #define STX_PCI_AFSR_S_PERR 0x0040000000000000ULL 133 #define STX_PCI_AFSR_S_TTO 0x0020000000000000ULL 134 #define STX_PCI_AFSR_S_UNUS 0x0010000000000000ULL 135 #define STX_PCI_AFSR_DWMASK 0x0000030000000000ULL 136 #define STX_PCI_AFSR_BMASK 0x000000ff00000000ULL 137 #define STX_PCI_AFSR_BLK 0x0000000080000000ULL 138 #define STX_PCI_AFSR_CFG 0x0000000040000000ULL 139 #define STX_PCI_AFSR_MEM 0x0000000020000000ULL 140 #define STX_PCI_AFSR_IO 0x0000000010000000ULL 141 142 /* PCI diagnostic register */ 143 #define SCZ_PCI_DIAG_BADECC_DIS 0x0000000000000400ULL 144 #define STX_PCI_DIAG_BYPASS_DIS 0x0000000000000200ULL 145 #define STX_PCI_DIAG_TTO_DIS 0x0000000000000100ULL 146 #define SCZ_PCI_DIAG_RTRYARB_DIS 0x0000000000000080ULL 147 #define STX_PCI_DIAG_RETRY_DIS 0x0000000000000040ULL 148 #define STX_PCI_DIAG_INTRSYNC_DIS 0x0000000000000020ULL 149 #define STX_PCI_DIAG_DMAPARITY_INV 0x0000000000000008ULL 150 #define STX_PCI_DIAG_PIODPARITY_INV 0x0000000000000004ULL 151 #define STX_PCI_DIAG_PIOAPARITY_INV 0x0000000000000002ULL 152 153 /* Tomatillo I/O cache register */ 154 #define TOM_PCI_IOC_PW 0x0000000000080000ULL 155 #define TOM_PCI_IOC_PRM 0x0000000000040000ULL 156 #define TOM_PCI_IOC_PRO 0x0000000000020000ULL 157 #define TOM_PCI_IOC_PRL 0x0000000000010000ULL 158 #define TOM_PCI_IOC_PRM_LEN 0x000000000000c000ULL 159 #define TOM_PCI_IOC_PRM_LEN_SHIFT 14 160 #define TOM_PCI_IOC_PRO_LEN 0x0000000000003000ULL 161 #define TOM_PCI_IOC_PRO_LEN_SHIFT 12 162 #define TOM_PCI_IOC_PRL_LEN 0x0000000000000c00ULL 163 #define TOM_PCI_IOC_PRL_LEN_SHIFT 10 164 #define TOM_PCI_IOC_PREF_OFF 0x0000000000000038ULL 165 #define TOM_PCI_IOC_PREF_OFF_SHIFT 3 166 #define TOM_PCI_IOC_CPRM 0x0000000000000004ULL 167 #define TOM_PCI_IOC_CPRO 0x0000000000000002ULL 168 #define TOM_PCI_IOC_CPRL 0x0000000000000001ULL 169 170 /* XMITS PCI-X error status register */ 171 #define XMS_PCI_X_ERR_STAT_P_SC_DSCRD 0x8000000000000000ULL 172 #define XMS_PCI_X_ERR_STAT_P_SC_TTO 0x4000000000000000ULL 173 #define XMS_PCI_X_ERR_STAT_P_SDSTAT 0x2000000000000000ULL 174 #define XMS_PCI_X_ERR_STAT_P_SMMU 0x1000000000000000ULL 175 #define XMS_PCI_X_ERR_STAT_P_CDSTAT 0x0800000000000000ULL 176 #define XMS_PCI_X_ERR_STAT_P_CMMU 0x0400000000000000ULL 177 #define XMS_PCI_X_ERR_STAT_S_SC_DSCRD 0x0080000000000000ULL 178 #define XMS_PCI_X_ERR_STAT_S_SC_TTO 0x0040000000000000ULL 179 #define XMS_PCI_X_ERR_STAT_S_SDSTAT 0x0020000000000000ULL 180 #define XMS_PCI_X_ERR_STAT_S_SMMU 0x0010000000000000ULL 181 #define XMS_PCI_X_ERR_STAT_S_CDSTAT 0x0008000000000000ULL 182 #define XMS_PCI_X_ERR_STAT_S_CMMU 0x0004000000000000ULL 183 #define XMS_PCI_X_ERR_STAT_PERR_RCV_IEN 0x0000000400000000ULL 184 #define XMS_PCI_X_ERR_STAT_PERR_RCV 0x0000000200000000ULL 185 #define XMS_PCI_X_ERR_STAT_SERR_ON_PERR 0x0000000100000000ULL 186 187 /* XMITS PCI-X diagnostic register */ 188 #define XMS_PCI_X_DIAG_DIS_FAIR 0x0000000000080000ULL 189 #define XMS_PCI_X_DIAG_CRCQ_VALID 0x0000000000040000ULL 190 #define XMS_PCI_X_DIAG_SRCQ_ONE 0x0000000000000200ULL 191 #define XMS_PCI_X_DIAG_CRCQ_FLUSH 0x0000000000000100ULL 192 #define XMS_PCI_X_DIAG_BUGCNTL_MASK 0x0000ffff00000000ULL 193 #define XMS_PCI_X_DIAG_BUGCNTL_SHIFT 32 194 #define XMS_PCI_X_DIAG_SRCQ_MASK 0x00000000000000ffULL 195 196 /* Controller configuration and status registers */ 197 /* Note that these are shared on Schizo but per-PBM on Tomatillo. */ 198 #define STX_CTRL_BUS_ERRLOG 0x00018 199 #define STX_CTRL_ECCCTRL 0x00020 200 #define STX_CTRL_UE_AFSR 0x00030 201 #define STX_CTRL_UE_AFAR 0x00038 202 #define STX_CTRL_CE_AFSR 0x00040 203 #define STX_CTRL_CE_AFAR 0x00048 204 #define STX_CTRL_PERF 0x07000 205 #define STX_CTRL_PERF_CNT 0x07008 206 207 /* Safari/JBus error log register */ 208 #define STX_CTRL_BUS_ERRLOG_BADCMD 0x4000000000000000ULL 209 #define SCZ_CTRL_BUS_ERRLOG_SSMDIS 0x2000000000000000ULL 210 #define SCZ_CTRL_BUS_ERRLOG_BADMA 0x1000000000000000ULL 211 #define SCZ_CTRL_BUS_ERRLOG_BADMB 0x0800000000000000ULL 212 #define SCZ_CTRL_BUS_ERRLOG_BADMC 0x0400000000000000ULL 213 #define TOM_CTRL_BUS_ERRLOG_SNOOP_GR 0x0000000000200000ULL 214 #define TOM_CTRL_BUS_ERRLOG_SNOOP_PCI 0x0000000000100000ULL 215 #define TOM_CTRL_BUS_ERRLOG_SNOOP_RD 0x0000000000080000ULL 216 #define TOM_CTRL_BUS_ERRLOG_SNOOP_RDS 0x0000000000020000ULL 217 #define TOM_CTRL_BUS_ERRLOG_SNOOP_RDSA 0x0000000000010000ULL 218 #define TOM_CTRL_BUS_ERRLOG_SNOOP_OWN 0x0000000000008000ULL 219 #define TOM_CTRL_BUS_ERRLOG_SNOOP_RDO 0x0000000000004000ULL 220 #define SCZ_CTRL_BUS_ERRLOG_CPU1PS 0x0000000000002000ULL 221 #define TOM_CTRL_BUS_ERRLOG_WDATA_PERR 0x0000000000002000ULL 222 #define SCZ_CTRL_BUS_ERRLOG_CPU1PB 0x0000000000001000ULL 223 #define TOM_CTRL_BUS_ERRLOG_CTRL_PERR 0x0000000000001000ULL 224 #define SCZ_CTRL_BUS_ERRLOG_CPU0PS 0x0000000000000800ULL 225 #define TOM_CTRL_BUS_ERRLOG_SNOOP_ERR 0x0000000000000800ULL 226 #define SCZ_CTRL_BUS_ERRLOG_CPU0PB 0x0000000000000400ULL 227 #define TOM_CTRL_BUS_ERRLOG_JBUS_ILL_B 0x0000000000000400ULL 228 #define SCZ_CTRL_BUS_ERRLOG_CIQTO 0x0000000000000200ULL 229 #define SCZ_CTRL_BUS_ERRLOG_LPQTO 0x0000000000000100ULL 230 #define TOM_CTRL_BUS_ERRLOG_JBUS_ILL_C 0x0000000000000100ULL 231 #define SCZ_CTRL_BUS_ERRLOG_SFPQTO 0x0000000000000080ULL 232 #define SCZ_CTRL_BUS_ERRLOG_UFPQTO 0x0000000000000040ULL 233 #define TOM_CTRL_BUS_ERRLOG_RD_PERR 0x0000000000000040ULL 234 #define STX_CTRL_BUS_ERRLOG_APERR 0x0000000000000020ULL 235 #define STX_CTRL_BUS_ERRLOG_UNMAP 0x0000000000000010ULL 236 #define STX_CTRL_BUS_ERRLOG_BUSERR 0x0000000000000004ULL 237 #define STX_CTRL_BUS_ERRLOG_TIMEOUT 0x0000000000000002ULL 238 #define SCZ_CTRL_BUS_ERRLOG_ILL 0x0000000000000001ULL 239 240 /* ECC control register */ 241 #define STX_CTRL_ECCCTRL_EE 0x8000000000000000ULL 242 #define STX_CTRL_ECCCTRL_UE 0x4000000000000000ULL 243 #define STX_CTRL_ECCCTRL_CE 0x2000000000000000ULL 244 245 /* Uncorrectable error asynchronous fault status register */ 246 #define STX_CTRL_UE_AFSR_P_PIO 0x8000000000000000ULL 247 #define STX_CTRL_UE_AFSR_P_DRD 0x4000000000000000ULL 248 #define STX_CTRL_UE_AFSR_P_DWR 0x2000000000000000ULL 249 #define STX_CTRL_UE_AFSR_S_PIO 0x1000000000000000ULL 250 #define STX_CTRL_UE_AFSR_S_DRD 0x0800000000000000ULL 251 #define STX_CTRL_UE_AFSR_S_DWR 0x0400000000000000ULL 252 #define STX_CTRL_UE_AFSR_ERRPNDG 0x0300000000000000ULL 253 #define STX_CTRL_UE_AFSR_BMASK 0x000003ff00000000ULL 254 #define STX_CTRL_UE_AFSR_QOFF 0x00000000c0000000ULL 255 #define STX_CTRL_UE_AFSR_AID 0x000000001f000000ULL 256 #define STX_CTRL_UE_AFSR_PARTIAL 0x0000000000800000ULL 257 #define STX_CTRL_UE_AFSR_OWNEDIN 0x0000000000400000ULL 258 #define STX_CTRL_UE_AFSR_MTAGSYND 0x00000000000f0000ULL 259 #define STX_CTRL_UE_AFSR_MTAG 0x000000000000e000ULL 260 #define STX_CTRL_UE_AFSR_ECCSYND 0x00000000000001ffULL 261 262 /* Correctable error asynchronous fault status register */ 263 #define STX_CTRL_CE_AFSR_P_PIO 0x8000000000000000ULL 264 #define STX_CTRL_CE_AFSR_P_DRD 0x4000000000000000ULL 265 #define STX_CTRL_CE_AFSR_P_DWR 0x2000000000000000ULL 266 #define STX_CTRL_CE_AFSR_S_PIO 0x1000000000000000ULL 267 #define STX_CTRL_CE_AFSR_S_DRD 0x0800000000000000ULL 268 #define STX_CTRL_CE_AFSR_S_DWR 0x0400000000000000ULL 269 #define STX_CTRL_CE_AFSR_ERRPNDG 0x0300000000000000ULL 270 #define STX_CTRL_CE_AFSR_BMASK 0x000003ff00000000ULL 271 #define STX_CTRL_CE_AFSR_QOFF 0x00000000c0000000ULL 272 #define STX_CTRL_CE_AFSR_AID 0x000000001f000000ULL 273 #define STX_CTRL_CE_AFSR_PARTIAL 0x0000000000800000ULL 274 #define STX_CTRL_CE_AFSR_OWNEDIN 0x0000000000400000ULL 275 #define STX_CTRL_CE_AFSR_MTAGSYND 0x00000000000f0000ULL 276 #define STX_CTRL_CE_AFSR_MTAG 0x000000000000e000ULL 277 #define STX_CTRL_CE_AFSR_ECCSYND 0x00000000000001ffULL 278 279 /* 280 * Safari/JBus performance control register 281 * NB: For Tomatillo only events 0x00 through 0x08 are documented as 282 * implemented. 283 */ 284 #define SCZ_CTRL_PERF_ZDATA_OUT 0x0000000000000016ULL 285 #define SCZ_CTRL_PERF_ZDATA_IN 0x0000000000000015ULL 286 #define SCZ_CTRL_PERF_ORQFULL 0x0000000000000014ULL 287 #define SCZ_CTRL_PERF_DVMA_WR 0x0000000000000013ULL 288 #define SCZ_CTRL_PERF_DVMA_RD 0x0000000000000012ULL 289 #define SCZ_CTRL_PERF_CYCPSESYS 0x0000000000000011ULL 290 #define STX_CTRL_PERF_PCI_B 0x000000000000000fULL 291 #define STX_CTRL_PERF_PCI_A 0x000000000000000eULL 292 #define STX_CTRL_PERF_UPA 0x000000000000000dULL 293 #define STX_CTRL_PERF_PIOINTRNL 0x000000000000000cULL 294 #define TOM_CTRL_PERF_WRI_WRIS 0x000000000000000bULL 295 #define STX_CTRL_PERF_INTRS 0x000000000000000aULL 296 #define STX_CTRL_PERF_PRTLWRMRGBUF 0x0000000000000009ULL 297 #define STX_CTRL_PERF_FGN_IO_HITS 0x0000000000000008ULL 298 #define STX_CTRL_PERF_FGN_IO_TRNS 0x0000000000000007ULL 299 #define STX_CTRL_PERF_OWN_CHRNT_HITS 0x0000000000000006ULL 300 #define STX_CTRL_PERF_OWN_CHRNT_TRNS 0x0000000000000005ULL 301 #define SCZ_CTRL_PERF_FGN_CHRNT_HITS 0x0000000000000004ULL 302 #define STX_CTRL_PERF_FGN_CHRNT_TRNS 0x0000000000000003ULL 303 #define STX_CTRL_PERF_CYCLES_PAUSE 0x0000000000000002ULL 304 #define STX_CTRL_PERF_BUSCYC 0x0000000000000001ULL 305 #define STX_CTRL_PERF_DIS 0x0000000000000000ULL 306 #define STX_CTRL_PERF_CNT1_SHIFT 11 307 #define STX_CTRL_PERF_CNT0_SHIFT 4 308 309 /* Safari/JBus performance counter register */ 310 #define STX_CTRL_PERF_CNT_MASK 0x00000000ffffffffULL 311 #define STX_CTRL_PERF_CNT_CNT1_SHIFT 32 312 #define STX_CTRL_PERF_CNT_CNT0_SHIFT 0 313 314 /* INO defines */ 315 #define STX_FB0_INO 0x2a /* FB0 int. shared w/ UPA64s */ 316 #define STX_FB1_INO 0x2b /* FB1 int. shared w/ UPA64s */ 317 #define STX_UE_INO 0x30 /* uncorrectable error */ 318 #define STX_CE_INO 0x31 /* correctable error */ 319 #define STX_PCIERR_A_INO 0x32 /* PCI bus A error */ 320 #define STX_PCIERR_B_INO 0x33 /* PCI bus B error */ 321 #define STX_BUS_INO 0x34 /* Safari/JBus error */ 322 #define STX_CDMA_A_INO 0x35 /* PCI bus A CDMA */ 323 #define STX_CDMA_B_INO 0x36 /* PCI bus B CDMA */ 324 #define STX_MAX_INO 0x37 325 326 /* Device space defines */ 327 #define STX_CONF_SIZE 0x1000000 328 #define STX_CONF_BUS_SHIFT 16 329 #define STX_CONF_DEV_SHIFT 11 330 #define STX_CONF_FUNC_SHIFT 8 331 #define STX_CONF_REG_SHIFT 0 332 #define STX_IO_SIZE 0x1000000 333 #define STX_MEM_SIZE 0x100000000 334 335 #define STX_CONF_OFF(bus, slot, func, reg) \ 336 (((bus) << STX_CONF_BUS_SHIFT) | \ 337 ((slot) << STX_CONF_DEV_SHIFT) | \ 338 ((func) << STX_CONF_FUNC_SHIFT) | \ 339 ((reg) << STX_CONF_REG_SHIFT)) 340 341 /* Definitions for the Schizo/Tomatillo configuration space */ 342 #define STX_CS_DEVICE 0 /* bridge CS device number */ 343 #define STX_CS_FUNC 0 /* brdige CS function number */ 344 345 /* Non-Standard registers in the configration space */ 346 /* 347 * NB: For Tomatillo the secondary and subordinate bus number registers 348 * apparently are read-only although documented otherwise; writing to 349 * them just triggers a PCI bus error interrupt or has no effect at best. 350 */ 351 #define STX_CSR_SECBUS 0x40 /* secondary bus number */ 352 #define STX_CSR_SUBBUS 0x41 /* subordinate bus number */ 353 354 /* Width of the physical addresses the IOMMU translates to */ 355 #define STX_IOMMU_BITS 43 356 357 #endif /* !_SPARC64_PCI_SCHIZOREG_H_ */ 358