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Searched refs:WREG32_P (Results 1 – 10 of 10) sorted by relevance

/freebsd-10-stable/sys/dev/drm2/radeon/
Dr600_hdmi.c313 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, in r600_hdmi_audio_workaround()
467 WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f); in r600_hdmi_update_audio_settings()
500 WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN, in r600_hdmi_enable()
505 WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN, in r600_hdmi_enable()
510 WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN); in r600_hdmi_enable()
567 WREG32_P(AVIVO_TMDSA_CNTL, 0, in r600_hdmi_disable()
571 WREG32_P(AVIVO_LVTMA_CNTL, 0, in r600_hdmi_disable()
575 WREG32_P(DDIA_CNTL, 0, ~DDIA_HDMI_EN); in r600_hdmi_disable()
Dr600_audio.c164 WREG32_P(R600_AUDIO_ENABLE, in r600_audio_engine_enable()
204 WREG32_P(R600_AUDIO_TIMING, 0, ~0x301); in r600_audio_set_clock()
210 WREG32_P(R600_AUDIO_TIMING, 0x100, ~0x301); in r600_audio_set_clock()
Dradeon_legacy_crtc.c331 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); in radeon_crtc_dpms()
333 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | in radeon_crtc_dpms()
335 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); in radeon_crtc_dpms()
345 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); in radeon_crtc_dpms()
347 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | in radeon_crtc_dpms()
349 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); in radeon_crtc_dpms()
913 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
934 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
Dradeon_legacy_encoders.c617 WREG32_P(RADEON_DAC_CNTL, in radeon_legacy_primary_dac_mode_set()
1281 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); in radeon_legacy_tv_dac_mode_set()
1318 WREG32_P(RADEON_GPIOPAD_A, 0, ~1); in r300_legacy_tv_detect()
1368 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); in r300_legacy_tv_detect()
1609 WREG32_P(RADEON_GPIOPAD_A, 1, ~1); in radeon_legacy_tv_dac_detect()
1665 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); in radeon_legacy_tv_dac_detect()
Dradeon_cursor.c121 WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN | in radeon_show_cursor()
Dni.c1177 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA); in cayman_cp_resume()
1184 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA); in cayman_cp_resume()
Dradeon.h1704 #define WREG32_P(reg, val, mask) \ macro
Devergreen.c3315 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); in evergreen_irq_process()
Dsi.c3975 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); in si_irq_process()
Dr100.c2858 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, in r100_get_accessible_vram()