1 /*-
2 * Copyright (c) 2011
3 * Ben Gray <ben.r.gray@gmail.com>.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 /**
29 * Very simple GPIO (general purpose IO) driver module for TI OMAP SoC's.
30 *
31 * Currently this driver only does the basics, get a value on a pin & set a
32 * value on a pin. Hopefully over time I'll expand this to be a bit more generic
33 * and support interrupts and other various bits on the SoC can do ... in the
34 * meantime this is all you get.
35 *
36 * Beware the OMA datasheet(s) lists GPIO banks 1-6, whereas I've used 0-5 here
37 * in the code.
38 *
39 *
40 */
41
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD: stable/10/sys/arm/ti/ti_gpio.c 278786 2015-02-14 21:16:19Z loos $");
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/bus.h>
48
49 #include <sys/kernel.h>
50 #include <sys/module.h>
51 #include <sys/rman.h>
52 #include <sys/lock.h>
53 #include <sys/mutex.h>
54 #include <sys/gpio.h>
55
56 #include <machine/bus.h>
57 #include <machine/resource.h>
58
59 #include <arm/ti/ti_scm.h>
60 #include <arm/ti/ti_prcm.h>
61
62 #include <dev/fdt/fdt_common.h>
63 #include <dev/ofw/openfirm.h>
64 #include <dev/ofw/ofw_bus.h>
65 #include <dev/ofw/ofw_bus_subr.h>
66
67 #include "gpio_if.h"
68
69 /* Register definitions */
70 #define TI_GPIO_REVISION 0x0000
71 #define TI_GPIO_SYSCONFIG 0x0010
72 #if defined(SOC_OMAP3)
73 #define TI_GPIO_SYSSTATUS 0x0014
74 #define TI_GPIO_IRQSTATUS1 0x0018
75 #define TI_GPIO_IRQENABLE1 0x001C
76 #define TI_GPIO_WAKEUPENABLE 0x0020
77 #define TI_GPIO_IRQSTATUS2 0x0028
78 #define TI_GPIO_IRQENABLE2 0x002C
79 #define TI_GPIO_CTRL 0x0030
80 #define TI_GPIO_OE 0x0034
81 #define TI_GPIO_DATAIN 0x0038
82 #define TI_GPIO_DATAOUT 0x003C
83 #define TI_GPIO_LEVELDETECT0 0x0040
84 #define TI_GPIO_LEVELDETECT1 0x0044
85 #define TI_GPIO_RISINGDETECT 0x0048
86 #define TI_GPIO_FALLINGDETECT 0x004C
87 #define TI_GPIO_DEBOUNCENABLE 0x0050
88 #define TI_GPIO_DEBOUNCINGTIME 0x0054
89 #define TI_GPIO_CLEARIRQENABLE1 0x0060
90 #define TI_GPIO_SETIRQENABLE1 0x0064
91 #define TI_GPIO_CLEARIRQENABLE2 0x0070
92 #define TI_GPIO_SETIRQENABLE2 0x0074
93 #define TI_GPIO_CLEARWKUENA 0x0080
94 #define TI_GPIO_SETWKUENA 0x0084
95 #define TI_GPIO_CLEARDATAOUT 0x0090
96 #define TI_GPIO_SETDATAOUT 0x0094
97 #elif defined(SOC_OMAP4) || defined(SOC_TI_AM335X)
98 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024
99 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028
100 #define TI_GPIO_IRQSTATUS_0 0x002C
101 #define TI_GPIO_IRQSTATUS_1 0x0030
102 #define TI_GPIO_IRQSTATUS_SET_0 0x0034
103 #define TI_GPIO_IRQSTATUS_SET_1 0x0038
104 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C
105 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040
106 #define TI_GPIO_IRQWAKEN_0 0x0044
107 #define TI_GPIO_IRQWAKEN_1 0x0048
108 #define TI_GPIO_SYSSTATUS 0x0114
109 #define TI_GPIO_IRQSTATUS1 0x0118
110 #define TI_GPIO_IRQENABLE1 0x011C
111 #define TI_GPIO_WAKEUPENABLE 0x0120
112 #define TI_GPIO_IRQSTATUS2 0x0128
113 #define TI_GPIO_IRQENABLE2 0x012C
114 #define TI_GPIO_CTRL 0x0130
115 #define TI_GPIO_OE 0x0134
116 #define TI_GPIO_DATAIN 0x0138
117 #define TI_GPIO_DATAOUT 0x013C
118 #define TI_GPIO_LEVELDETECT0 0x0140
119 #define TI_GPIO_LEVELDETECT1 0x0144
120 #define TI_GPIO_RISINGDETECT 0x0148
121 #define TI_GPIO_FALLINGDETECT 0x014C
122 #define TI_GPIO_DEBOUNCENABLE 0x0150
123 #define TI_GPIO_DEBOUNCINGTIME 0x0154
124 #define TI_GPIO_CLEARWKUPENA 0x0180
125 #define TI_GPIO_SETWKUENA 0x0184
126 #define TI_GPIO_CLEARDATAOUT 0x0190
127 #define TI_GPIO_SETDATAOUT 0x0194
128 #else
129 #error "Unknown SoC"
130 #endif
131
132 /* Other SoC Specific definitions */
133 #if defined(SOC_OMAP3)
134 #define MAX_GPIO_BANKS 6
135 #define FIRST_GPIO_BANK 1
136 #define INTR_PER_BANK 1
137 #define TI_GPIO_REV 0x00000025
138 #elif defined(SOC_OMAP4)
139 #define MAX_GPIO_BANKS 6
140 #define FIRST_GPIO_BANK 1
141 #define INTR_PER_BANK 1
142 #define TI_GPIO_REV 0x50600801
143 #elif defined(SOC_TI_AM335X)
144 #define MAX_GPIO_BANKS 4
145 #define FIRST_GPIO_BANK 0
146 #define INTR_PER_BANK 2
147 #define TI_GPIO_REV 0x50600801
148 #endif
149 #define PINS_PER_BANK 32
150 #define MAX_GPIO_INTRS MAX_GPIO_BANKS * INTR_PER_BANK
151
152 /**
153 * ti_gpio_mem_spec - Resource specification used when allocating resources
154 * ti_gpio_irq_spec - Resource specification used when allocating resources
155 *
156 * This driver module can have up to six independent memory regions, each
157 * region typically controls 32 GPIO pins.
158 *
159 * On OMAP3 and OMAP4 there is only one physical interrupt line per bank,
160 * but there are two set of registers which control the interrupt delivery
161 * to internal subsystems. The first set of registers control the
162 * interrupts delivery to the MPU and the second set control the
163 * interrupts delivery to the DSP.
164 *
165 * On AM335x there are two physical interrupt lines for each GPIO module.
166 * Each interrupt line is controlled by a set of registers.
167 */
168 static struct resource_spec ti_gpio_mem_spec[] = {
169 { SYS_RES_MEMORY, 0, RF_ACTIVE },
170 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL },
171 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL },
172 { SYS_RES_MEMORY, 3, RF_ACTIVE | RF_OPTIONAL },
173 #if !defined(SOC_TI_AM335X)
174 { SYS_RES_MEMORY, 4, RF_ACTIVE | RF_OPTIONAL },
175 { SYS_RES_MEMORY, 5, RF_ACTIVE | RF_OPTIONAL },
176 #endif
177 { -1, 0, 0 }
178 };
179 static struct resource_spec ti_gpio_irq_spec[] = {
180 { SYS_RES_IRQ, 0, RF_ACTIVE },
181 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL },
182 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL },
183 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL },
184 { SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL },
185 { SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL },
186 #if defined(SOC_TI_AM335X)
187 { SYS_RES_IRQ, 6, RF_ACTIVE | RF_OPTIONAL },
188 { SYS_RES_IRQ, 7, RF_ACTIVE | RF_OPTIONAL },
189 #endif
190 { -1, 0, 0 }
191 };
192
193 /**
194 * Structure that stores the driver context.
195 *
196 * This structure is allocated during driver attach.
197 */
198 struct ti_gpio_softc {
199 device_t sc_dev;
200
201 /*
202 * The memory resource(s) for the PRCM register set, when the device is
203 * created the caller can assign up to 6 memory regions depending on
204 * the SoC type.
205 */
206 struct resource *sc_mem_res[MAX_GPIO_BANKS];
207 struct resource *sc_irq_res[MAX_GPIO_INTRS];
208
209 /* The handle for the register IRQ handlers. */
210 void *sc_irq_hdl[MAX_GPIO_INTRS];
211
212 /*
213 * The following describes the H/W revision of each of the GPIO banks.
214 */
215 uint32_t sc_revision[MAX_GPIO_BANKS];
216
217 struct mtx sc_mtx;
218 };
219
220 /**
221 * Macros for driver mutex locking
222 */
223 #define TI_GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
224 #define TI_GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
225 #define TI_GPIO_LOCK_INIT(_sc) \
226 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
227 "ti_gpio", MTX_DEF)
228 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx)
229 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
230 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED)
231
232 /**
233 * ti_gpio_read_4 - reads a 16-bit value from one of the PADCONFS registers
234 * @sc: GPIO device context
235 * @bank: The bank to read from
236 * @off: The offset of a register from the GPIO register address range
237 *
238 *
239 * RETURNS:
240 * 32-bit value read from the register.
241 */
242 static inline uint32_t
ti_gpio_read_4(struct ti_gpio_softc * sc,unsigned int bank,bus_size_t off)243 ti_gpio_read_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off)
244 {
245 return (bus_read_4(sc->sc_mem_res[bank], off));
246 }
247
248 /**
249 * ti_gpio_write_4 - writes a 32-bit value to one of the PADCONFS registers
250 * @sc: GPIO device context
251 * @bank: The bank to write to
252 * @off: The offset of a register from the GPIO register address range
253 * @val: The value to write into the register
254 *
255 * RETURNS:
256 * nothing
257 */
258 static inline void
ti_gpio_write_4(struct ti_gpio_softc * sc,unsigned int bank,bus_size_t off,uint32_t val)259 ti_gpio_write_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off,
260 uint32_t val)
261 {
262 bus_write_4(sc->sc_mem_res[bank], off, val);
263 }
264
265 static inline void
ti_gpio_intr_clr(struct ti_gpio_softc * sc,unsigned int bank,uint32_t mask)266 ti_gpio_intr_clr(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask)
267 {
268
269 /* We clear both set of registers. */
270 #if defined(SOC_OMAP4) || defined(SOC_TI_AM335X)
271 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_0, mask);
272 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_1, mask);
273 #else
274 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE1, mask);
275 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE2, mask);
276 #endif
277 }
278
279 /**
280 * ti_gpio_pin_max - Returns the maximum number of GPIO pins
281 * @dev: gpio device handle
282 * @maxpin: pointer to a value that upon return will contain the maximum number
283 * of pins in the device.
284 *
285 *
286 * LOCKING:
287 * Internally locks the context
288 *
289 * RETURNS:
290 * Returns 0 on success otherwise an error code
291 */
292 static int
ti_gpio_pin_max(device_t dev,int * maxpin)293 ti_gpio_pin_max(device_t dev, int *maxpin)
294 {
295 struct ti_gpio_softc *sc = device_get_softc(dev);
296 unsigned int i;
297 unsigned int banks = 0;
298
299 TI_GPIO_LOCK(sc);
300
301 /* Calculate how many valid banks we have and then multiply that by 32 to
302 * give use the total number of pins.
303 */
304 for (i = 0; i < MAX_GPIO_BANKS; i++) {
305 if (sc->sc_mem_res[i] != NULL)
306 banks++;
307 }
308
309 *maxpin = (banks * PINS_PER_BANK) - 1;
310
311 TI_GPIO_UNLOCK(sc);
312
313 return (0);
314 }
315
316 /**
317 * ti_gpio_pin_getcaps - Gets the capabilties of a given pin
318 * @dev: gpio device handle
319 * @pin: the number of the pin
320 * @caps: pointer to a value that upon return will contain the capabilities
321 *
322 * Currently all pins have the same capability, notably:
323 * - GPIO_PIN_INPUT
324 * - GPIO_PIN_OUTPUT
325 * - GPIO_PIN_PULLUP
326 * - GPIO_PIN_PULLDOWN
327 *
328 * LOCKING:
329 * Internally locks the context
330 *
331 * RETURNS:
332 * Returns 0 on success otherwise an error code
333 */
334 static int
ti_gpio_pin_getcaps(device_t dev,uint32_t pin,uint32_t * caps)335 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
336 {
337 struct ti_gpio_softc *sc = device_get_softc(dev);
338 uint32_t bank = (pin / PINS_PER_BANK);
339
340 TI_GPIO_LOCK(sc);
341
342 /* Sanity check the pin number is valid */
343 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
344 TI_GPIO_UNLOCK(sc);
345 return (EINVAL);
346 }
347
348 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |GPIO_PIN_PULLUP |
349 GPIO_PIN_PULLDOWN);
350
351 TI_GPIO_UNLOCK(sc);
352
353 return (0);
354 }
355
356 /**
357 * ti_gpio_pin_getflags - Gets the current flags of a given pin
358 * @dev: gpio device handle
359 * @pin: the number of the pin
360 * @flags: upon return will contain the current flags of the pin
361 *
362 * Reads the current flags of a given pin, here we actually read the H/W
363 * registers to determine the flags, rather than storing the value in the
364 * setflags call.
365 *
366 * LOCKING:
367 * Internally locks the context
368 *
369 * RETURNS:
370 * Returns 0 on success otherwise an error code
371 */
372 static int
ti_gpio_pin_getflags(device_t dev,uint32_t pin,uint32_t * flags)373 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
374 {
375 struct ti_gpio_softc *sc = device_get_softc(dev);
376 uint32_t bank = (pin / PINS_PER_BANK);
377
378 TI_GPIO_LOCK(sc);
379
380 /* Sanity check the pin number is valid */
381 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
382 TI_GPIO_UNLOCK(sc);
383 return (EINVAL);
384 }
385
386 /* Get the current pin state */
387 ti_scm_padconf_get_gpioflags(pin, flags);
388
389 TI_GPIO_UNLOCK(sc);
390
391 return (0);
392 }
393
394 /**
395 * ti_gpio_pin_getname - Gets the name of a given pin
396 * @dev: gpio device handle
397 * @pin: the number of the pin
398 * @name: buffer to put the name in
399 *
400 * The driver simply calls the pins gpio_n, where 'n' is obviously the number
401 * of the pin.
402 *
403 * LOCKING:
404 * Internally locks the context
405 *
406 * RETURNS:
407 * Returns 0 on success otherwise an error code
408 */
409 static int
ti_gpio_pin_getname(device_t dev,uint32_t pin,char * name)410 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
411 {
412 struct ti_gpio_softc *sc = device_get_softc(dev);
413 uint32_t bank = (pin / PINS_PER_BANK);
414
415 TI_GPIO_LOCK(sc);
416
417 /* Sanity check the pin number is valid */
418 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
419 TI_GPIO_UNLOCK(sc);
420 return (EINVAL);
421 }
422
423 /* Set a very simple name */
424 snprintf(name, GPIOMAXNAME, "gpio_%u", pin);
425 name[GPIOMAXNAME - 1] = '\0';
426
427 TI_GPIO_UNLOCK(sc);
428
429 return (0);
430 }
431
432 /**
433 * ti_gpio_pin_setflags - Sets the flags for a given pin
434 * @dev: gpio device handle
435 * @pin: the number of the pin
436 * @flags: the flags to set
437 *
438 * The flags of the pin correspond to things like input/output mode, pull-ups,
439 * pull-downs, etc. This driver doesn't support all flags, only the following:
440 * - GPIO_PIN_INPUT
441 * - GPIO_PIN_OUTPUT
442 * - GPIO_PIN_PULLUP
443 * - GPIO_PIN_PULLDOWN
444 *
445 * LOCKING:
446 * Internally locks the context
447 *
448 * RETURNS:
449 * Returns 0 on success otherwise an error code
450 */
451 static int
ti_gpio_pin_setflags(device_t dev,uint32_t pin,uint32_t flags)452 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
453 {
454 struct ti_gpio_softc *sc = device_get_softc(dev);
455 uint32_t bank = (pin / PINS_PER_BANK);
456 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
457 uint32_t reg_val;
458
459 TI_GPIO_LOCK(sc);
460
461 /* Sanity check the pin number is valid */
462 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
463 TI_GPIO_UNLOCK(sc);
464 return (EINVAL);
465 }
466
467 /* Set the GPIO mode and state */
468 if (ti_scm_padconf_set_gpioflags(pin, flags) != 0) {
469 TI_GPIO_UNLOCK(sc);
470 return (EINVAL);
471 }
472
473 /* If configuring as an output set the "output enable" bit */
474 reg_val = ti_gpio_read_4(sc, bank, TI_GPIO_OE);
475 if (flags & GPIO_PIN_INPUT)
476 reg_val |= mask;
477 else
478 reg_val &= ~mask;
479 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_val);
480
481 TI_GPIO_UNLOCK(sc);
482
483 return (0);
484 }
485
486 /**
487 * ti_gpio_pin_set - Sets the current level on a GPIO pin
488 * @dev: gpio device handle
489 * @pin: the number of the pin
490 * @value: non-zero value will drive the pin high, otherwise the pin is
491 * driven low.
492 *
493 *
494 * LOCKING:
495 * Internally locks the context
496 *
497 * RETURNS:
498 * Returns 0 on success otherwise a error code
499 */
500 static int
ti_gpio_pin_set(device_t dev,uint32_t pin,unsigned int value)501 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
502 {
503 struct ti_gpio_softc *sc = device_get_softc(dev);
504 uint32_t bank = (pin / PINS_PER_BANK);
505 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
506
507 TI_GPIO_LOCK(sc);
508
509 /* Sanity check the pin number is valid */
510 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
511 TI_GPIO_UNLOCK(sc);
512 return (EINVAL);
513 }
514
515 ti_gpio_write_4(sc, bank, (value == GPIO_PIN_LOW) ? TI_GPIO_CLEARDATAOUT
516 : TI_GPIO_SETDATAOUT, mask);
517
518 TI_GPIO_UNLOCK(sc);
519
520 return (0);
521 }
522
523 /**
524 * ti_gpio_pin_get - Gets the current level on a GPIO pin
525 * @dev: gpio device handle
526 * @pin: the number of the pin
527 * @value: pointer to a value that upond return will contain the pin value
528 *
529 * The pin must be configured as an input pin beforehand, otherwise this
530 * function will fail.
531 *
532 * LOCKING:
533 * Internally locks the context
534 *
535 * RETURNS:
536 * Returns 0 on success otherwise a error code
537 */
538 static int
ti_gpio_pin_get(device_t dev,uint32_t pin,unsigned int * value)539 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
540 {
541 struct ti_gpio_softc *sc = device_get_softc(dev);
542 uint32_t bank = (pin / PINS_PER_BANK);
543 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
544 uint32_t val = 0;
545
546 TI_GPIO_LOCK(sc);
547
548 /* Sanity check the pin number is valid */
549 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
550 TI_GPIO_UNLOCK(sc);
551 return (EINVAL);
552 }
553
554 /* Sanity check the pin is not configured as an output */
555 val = ti_gpio_read_4(sc, bank, TI_GPIO_OE);
556
557 /* Read the value on the pin */
558 if (val & mask)
559 *value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAIN) & mask) ? 1 : 0;
560 else
561 *value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT) & mask) ? 1 : 0;
562
563 TI_GPIO_UNLOCK(sc);
564
565 return (0);
566 }
567
568 /**
569 * ti_gpio_pin_toggle - Toggles a given GPIO pin
570 * @dev: gpio device handle
571 * @pin: the number of the pin
572 *
573 *
574 * LOCKING:
575 * Internally locks the context
576 *
577 * RETURNS:
578 * Returns 0 on success otherwise a error code
579 */
580 static int
ti_gpio_pin_toggle(device_t dev,uint32_t pin)581 ti_gpio_pin_toggle(device_t dev, uint32_t pin)
582 {
583 struct ti_gpio_softc *sc = device_get_softc(dev);
584 uint32_t bank = (pin / PINS_PER_BANK);
585 uint32_t mask = (1UL << (pin % PINS_PER_BANK));
586 uint32_t val;
587
588 TI_GPIO_LOCK(sc);
589
590 /* Sanity check the pin number is valid */
591 if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) {
592 TI_GPIO_UNLOCK(sc);
593 return (EINVAL);
594 }
595
596 /* Toggle the pin */
597 val = ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT);
598 if (val & mask)
599 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARDATAOUT, mask);
600 else
601 ti_gpio_write_4(sc, bank, TI_GPIO_SETDATAOUT, mask);
602
603 TI_GPIO_UNLOCK(sc);
604
605 return (0);
606 }
607
608 /**
609 * ti_gpio_intr - ISR for all GPIO modules
610 * @arg: the soft context pointer
611 *
612 * Unsused
613 *
614 * LOCKING:
615 * Internally locks the context
616 *
617 */
618 static void
ti_gpio_intr(void * arg)619 ti_gpio_intr(void *arg)
620 {
621 struct ti_gpio_softc *sc = arg;
622
623 TI_GPIO_LOCK(sc);
624 /* TODO: something useful */
625 TI_GPIO_UNLOCK(sc);
626 }
627
628 /**
629 * ti_gpio_probe - probe function for the driver
630 * @dev: gpio device handle
631 *
632 * Simply sets the name of the driver
633 *
634 * LOCKING:
635 * None
636 *
637 * RETURNS:
638 * Always returns 0
639 */
640 static int
ti_gpio_probe(device_t dev)641 ti_gpio_probe(device_t dev)
642 {
643
644 if (!ofw_bus_status_okay(dev))
645 return (ENXIO);
646
647 if (!ofw_bus_is_compatible(dev, "ti,gpio"))
648 return (ENXIO);
649
650 device_set_desc(dev, "TI General Purpose I/O (GPIO)");
651
652 return (0);
653 }
654
655 static int
ti_gpio_attach_intr(device_t dev)656 ti_gpio_attach_intr(device_t dev)
657 {
658 int i;
659 struct ti_gpio_softc *sc;
660
661 sc = device_get_softc(dev);
662 for (i = 0; i < MAX_GPIO_INTRS; i++) {
663 if (sc->sc_irq_res[i] == NULL)
664 break;
665
666 /*
667 * Register our interrupt handler for each of the IRQ resources.
668 */
669 if (bus_setup_intr(dev, sc->sc_irq_res[i],
670 INTR_TYPE_MISC | INTR_MPSAFE, NULL, ti_gpio_intr, sc,
671 &sc->sc_irq_hdl[i]) != 0) {
672 device_printf(dev,
673 "WARNING: unable to register interrupt handler\n");
674 return (-1);
675 }
676 }
677
678 return (0);
679 }
680
681 static int
ti_gpio_detach_intr(device_t dev)682 ti_gpio_detach_intr(device_t dev)
683 {
684 int i;
685 struct ti_gpio_softc *sc;
686
687 /* Teardown our interrupt handlers. */
688 sc = device_get_softc(dev);
689 for (i = 0; i < MAX_GPIO_INTRS; i++) {
690 if (sc->sc_irq_res[i] == NULL)
691 break;
692
693 if (sc->sc_irq_hdl[i]) {
694 bus_teardown_intr(dev, sc->sc_irq_res[i],
695 sc->sc_irq_hdl[i]);
696 }
697 }
698
699 return (0);
700 }
701
702 static int
ti_gpio_bank_init(device_t dev,int bank)703 ti_gpio_bank_init(device_t dev, int bank)
704 {
705 int pin;
706 struct ti_gpio_softc *sc;
707 uint32_t flags, reg_oe;
708
709 sc = device_get_softc(dev);
710
711 /* Enable the interface and functional clocks for the module. */
712 ti_prcm_clk_enable(GPIO0_CLK + FIRST_GPIO_BANK + bank);
713
714 /*
715 * Read the revision number of the module. TI don't publish the
716 * actual revision numbers, so instead the values have been
717 * determined by experimentation.
718 */
719 sc->sc_revision[bank] = ti_gpio_read_4(sc, bank, TI_GPIO_REVISION);
720
721 /* Check the revision. */
722 if (sc->sc_revision[bank] != TI_GPIO_REV) {
723 device_printf(dev, "Warning: could not determine the revision "
724 "of %u GPIO module (revision:0x%08x)\n",
725 bank, sc->sc_revision[bank]);
726 return (EINVAL);
727 }
728
729 /* Disable interrupts for all pins. */
730 ti_gpio_intr_clr(sc, bank, 0xffffffff);
731
732 /* Init OE register based on pads configuration. */
733 reg_oe = 0xffffffff;
734 for (pin = 0; pin < PINS_PER_BANK; pin++) {
735 ti_scm_padconf_get_gpioflags(PINS_PER_BANK * bank + pin,
736 &flags);
737 if (flags & GPIO_PIN_OUTPUT)
738 reg_oe &= ~(1UL << pin);
739 }
740 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_oe);
741
742 return (0);
743 }
744
745 /**
746 * ti_gpio_attach - attach function for the driver
747 * @dev: gpio device handle
748 *
749 * Allocates and sets up the driver context for all GPIO banks. This function
750 * expects the memory ranges and IRQs to already be allocated to the driver.
751 *
752 * LOCKING:
753 * None
754 *
755 * RETURNS:
756 * Always returns 0
757 */
758 static int
ti_gpio_attach(device_t dev)759 ti_gpio_attach(device_t dev)
760 {
761 struct ti_gpio_softc *sc;
762 unsigned int i;
763 int err;
764
765 sc = device_get_softc(dev);
766 sc->sc_dev = dev;
767
768 TI_GPIO_LOCK_INIT(sc);
769
770 /* There are up to 6 different GPIO register sets located in different
771 * memory areas on the chip. The memory range should have been set for
772 * the driver when it was added as a child.
773 */
774 if (bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res) != 0) {
775 device_printf(dev, "Error: could not allocate mem resources\n");
776 return (ENXIO);
777 }
778
779 /* Request the IRQ resources */
780 if (bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res) != 0) {
781 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
782 device_printf(dev, "Error: could not allocate irq resources\n");
783 return (ENXIO);
784 }
785
786 /* Setup the IRQ resources */
787 if (ti_gpio_attach_intr(dev) != 0) {
788 ti_gpio_detach_intr(dev);
789 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
790 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
791 return (ENXIO);
792 }
793
794 /* We need to go through each block and ensure the clocks are running and
795 * the module is enabled. It might be better to do this only when the
796 * pins are configured which would result in less power used if the GPIO
797 * pins weren't used ...
798 */
799 for (i = 0; i < MAX_GPIO_BANKS; i++) {
800 if (sc->sc_mem_res[i] != NULL) {
801 /* Initialize the GPIO module. */
802 err = ti_gpio_bank_init(dev, i);
803 if (err != 0) {
804 ti_gpio_detach_intr(dev);
805 bus_release_resources(dev, ti_gpio_irq_spec,
806 sc->sc_irq_res);
807 bus_release_resources(dev, ti_gpio_mem_spec,
808 sc->sc_mem_res);
809 return (err);
810 }
811 }
812 }
813
814 /* Finish of the probe call */
815 device_add_child(dev, "gpioc", -1);
816 device_add_child(dev, "gpiobus", -1);
817
818 return (bus_generic_attach(dev));
819 }
820
821 /**
822 * ti_gpio_detach - detach function for the driver
823 * @dev: scm device handle
824 *
825 * Allocates and sets up the driver context, this simply entails creating a
826 * bus mappings for the SCM register set.
827 *
828 * LOCKING:
829 * None
830 *
831 * RETURNS:
832 * Always returns 0
833 */
834 static int
ti_gpio_detach(device_t dev)835 ti_gpio_detach(device_t dev)
836 {
837 struct ti_gpio_softc *sc = device_get_softc(dev);
838 unsigned int i;
839
840 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
841
842 /* Disable all interrupts */
843 for (i = 0; i < MAX_GPIO_BANKS; i++) {
844 if (sc->sc_mem_res[i] != NULL)
845 ti_gpio_intr_clr(sc, i, 0xffffffff);
846 }
847
848 bus_generic_detach(dev);
849
850 /* Release the memory and IRQ resources. */
851 ti_gpio_detach_intr(dev);
852 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
853 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
854
855 TI_GPIO_LOCK_DESTROY(sc);
856
857 return (0);
858 }
859
860 static phandle_t
ti_gpio_get_node(device_t bus,device_t dev)861 ti_gpio_get_node(device_t bus, device_t dev)
862 {
863
864 /* We only have one child, the GPIO bus, which needs our own node. */
865 return (ofw_bus_get_node(bus));
866 }
867
868 static device_method_t ti_gpio_methods[] = {
869 DEVMETHOD(device_probe, ti_gpio_probe),
870 DEVMETHOD(device_attach, ti_gpio_attach),
871 DEVMETHOD(device_detach, ti_gpio_detach),
872
873 /* GPIO protocol */
874 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max),
875 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname),
876 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags),
877 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps),
878 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags),
879 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get),
880 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set),
881 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle),
882
883 /* ofw_bus interface */
884 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node),
885
886 {0, 0},
887 };
888
889 static driver_t ti_gpio_driver = {
890 "gpio",
891 ti_gpio_methods,
892 sizeof(struct ti_gpio_softc),
893 };
894 static devclass_t ti_gpio_devclass;
895
896 DRIVER_MODULE(ti_gpio, simplebus, ti_gpio_driver, ti_gpio_devclass, 0, 0);
897