1 /*- 2 * Hitachi HD64570 serial communications adaptor registers. 3 * 4 * Copyright (C) 1996 Cronyx Engineering. 5 * Author: Serge Vakulenko, <vak@cronyx.ru> 6 * 7 * This software is distributed with NO WARRANTIES, not even the implied 8 * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 9 * 10 * Authors grant any other persons or organisations permission to use 11 * or modify this software as long as this message is kept with the software, 12 * all derivative works or modified versions. 13 * 14 * Cronyx Id: hdc64570.h,v 1.1.2.2 2003/11/12 17:31:21 rik Exp $ 15 * $FreeBSD: stable/10/sys/dev/ctau/hdc64570.h 139749 2005-01-06 01:43:34Z imp $ 16 */ 17 18 /* 19 * Low power mode control register. 20 */ 21 #define HD_LPR 0x00 /* low power register */ 22 23 /* 24 * Interrupt control registers. 25 */ 26 #define HD_IVR 0x1a /* interrupt vector register */ 27 #define HD_IMVR 0x1c /* interrupt modified vector register */ 28 #define HD_ITCR 0x18 /* interrupt control register */ 29 #define HD_ISR0 0x10 /* interrupt status register 0, ro */ 30 #define HD_ISR1 0x11 /* interrupt status register 1, ro */ 31 #define HD_ISR2 0x12 /* interrupt status register 2, ro */ 32 #define HD_IER0 0x14 /* interrupt enable register 0 */ 33 #define HD_IER1 0x15 /* interrupt enable register 1 */ 34 #define HD_IER2 0x16 /* interrupt enable register 2 */ 35 36 /* 37 * Multiprotocol serial communication interface registers. 38 */ 39 #define HD_MD0_0 0x2e /* mode register 0 chan 0 */ 40 #define HD_MD0_1 0x4e /* mode register 0 chan 1 */ 41 #define HD_MD1_0 0x2f /* mode register 1 chan 0 */ 42 #define HD_MD1_1 0x4f /* mode register 1 chan 1 */ 43 #define HD_MD2_0 0x30 /* mode register 2 chan 0 */ 44 #define HD_MD2_1 0x50 /* mode register 2 chan 1 */ 45 #define HD_CTL_0 0x31 /* control register chan 0 */ 46 #define HD_CTL_1 0x51 /* control register chan 1 */ 47 #define HD_RXS_0 0x36 /* RX clock source register chan 0 */ 48 #define HD_RXS_1 0x56 /* RX clock source register chan 1 */ 49 #define HD_TXS_0 0x37 /* TX clock source register chan 0 */ 50 #define HD_TXS_1 0x57 /* TX clock source register chan 1 */ 51 #define HD_TMC_0 0x35 /* time constant register chan 0 */ 52 #define HD_TMC_1 0x55 /* time constant register chan 1 */ 53 #define HD_CMD_0 0x2c /* command register chan 0, wo */ 54 #define HD_CMD_1 0x4c /* command register chan 1, wo */ 55 #define HD_ST0_0 0x22 /* status register 0 chan 0, ro */ 56 #define HD_ST0_1 0x42 /* status register 0 chan 1, ro */ 57 #define HD_ST1_0 0x23 /* status register 1 chan 0 */ 58 #define HD_ST1_1 0x43 /* status register 1 chan 1 */ 59 #define HD_ST2_0 0x24 /* status register 2 chan 0 */ 60 #define HD_ST2_1 0x44 /* status register 2 chan 1 */ 61 #define HD_ST3_0 0x25 /* status register 3 chan 0, ro */ 62 #define HD_ST3_1 0x45 /* status register 3 chan 1, ro */ 63 #define HD_FST_0 0x26 /* frame status register chan 0 */ 64 #define HD_FST_1 0x46 /* frame status register chan 1 */ 65 #define HD_IE0_0 0x28 /* interrupt enable register 0 chan 0 */ 66 #define HD_IE0_1 0x48 /* interrupt enable register 0 chan 1 */ 67 #define HD_IE1_0 0x29 /* interrupt enable register 1 chan 0 */ 68 #define HD_IE1_1 0x49 /* interrupt enable register 1 chan 1 */ 69 #define HD_IE2_0 0x2a /* interrupt enable register 2 chan 0 */ 70 #define HD_IE2_1 0x4a /* interrupt enable register 2 chan 1 */ 71 #define HD_FIE_0 0x2b /* frame interrupt enable register chan 0 */ 72 #define HD_FIE_1 0x4b /* frame interrupt enable register chan 1 */ 73 #define HD_SA0_0 0x32 /* sync/address register 0 chan 0 */ 74 #define HD_SA0_1 0x52 /* sync/address register 0 chan 1 */ 75 #define HD_SA1_0 0x33 /* sync/address register 1 chan 0 */ 76 #define HD_SA1_1 0x53 /* sync/address register 1 chan 1 */ 77 #define HD_IDL_0 0x34 /* idle pattern register chan 0 */ 78 #define HD_IDL_1 0x54 /* idle pattern register chan 1 */ 79 #define HD_TRB_0 0x20 /* TX/RX buffer register chan 0 */ 80 #define HD_TRB_1 0x40 /* TX/RX buffer register chan 1 */ 81 #define HD_RRC_0 0x3a /* RX ready control register chan 0 */ 82 #define HD_RRC_1 0x5a /* RX ready control register chan 1 */ 83 #define HD_TRC0_0 0x38 /* TX ready control register 0 chan 0 */ 84 #define HD_TRC0_1 0x58 /* TX ready control register 0 chan 1 */ 85 #define HD_TRC1_0 0x39 /* TX ready control register 1 chan 0 */ 86 #define HD_TRC1_1 0x59 /* TX ready control register 1 chan 1 */ 87 #define HD_CST_0 0x3c /* current status register chan 0 */ 88 #define HD_CST_1 0x5c /* current status register chan 1 */ 89 90 /* 91 * DMA controller registers. 92 */ 93 #define HD_PCR 0x08 /* DMA priority control register */ 94 #define HD_DMER 0x09 /* DMA master enable register */ 95 96 #define HD_DAR_0R 0x80 /* destination address chan 0rx */ 97 #define HD_DAR_0T 0xa0 /* destination address chan 0tx */ 98 #define HD_DAR_1R 0xc0 /* destination address chan 1rx */ 99 #define HD_DAR_1T 0xe0 /* destination address chan 1tx */ 100 #define HD_DARB_0R 0x82 /* destination address B chan 0rx */ 101 #define HD_DARB_0T 0xa2 /* destination address B chan 0tx */ 102 #define HD_DARB_1R 0xc2 /* destination address B chan 1rx */ 103 #define HD_DARB_1T 0xe2 /* destination address B chan 1tx */ 104 #define HD_SAR_0R 0x84 /* source address chan 0rx */ 105 #define HD_SAR_0T 0xa4 /* source address chan 0tx */ 106 #define HD_SAR_1R 0xc4 /* source address chan 1rx */ 107 #define HD_SAR_1T 0xe4 /* source address chan 1tx */ 108 #define HD_SARB_0R 0x86 /* source address B chan 0rx */ 109 #define HD_SARB_0T 0xa6 /* source address B chan 0tx */ 110 #define HD_SARB_1R 0xc6 /* source address B chan 1rx */ 111 #define HD_SARB_1T 0xe6 /* source address B chan 1tx */ 112 #define HD_CDA_0R 0x88 /* current descriptor address chan 0rx */ 113 #define HD_CDA_0T 0xa8 /* current descriptor address chan 0tx */ 114 #define HD_CDA_1R 0xc8 /* current descriptor address chan 1rx */ 115 #define HD_CDA_1T 0xe8 /* current descriptor address chan 1tx */ 116 #define HD_EDA_0R 0x8a /* error descriptor address chan 0rx */ 117 #define HD_EDA_0T 0xaa /* error descriptor address chan 0tx */ 118 #define HD_EDA_1R 0xca /* error descriptor address chan 1rx */ 119 #define HD_EDA_1T 0xea /* error descriptor address chan 1tx */ 120 #define HD_BFL_0R 0x8c /* receive buffer length chan 0rx */ 121 #define HD_BFL_1R 0xcc /* receive buffer length chan 1rx */ 122 #define HD_BCR_0R 0x8e /* byte count register chan 0rx */ 123 #define HD_BCR_0T 0xae /* byte count register chan 0tx */ 124 #define HD_BCR_1R 0xce /* byte count register chan 1rx */ 125 #define HD_BCR_1T 0xee /* byte count register chan 1tx */ 126 #define HD_DSR_0R 0x90 /* DMA status register chan 0rx */ 127 #define HD_DSR_0T 0xb0 /* DMA status register chan 0tx */ 128 #define HD_DSR_1R 0xd0 /* DMA status register chan 1rx */ 129 #define HD_DSR_1T 0xf0 /* DMA status register chan 1tx */ 130 #define HD_DMR_0R 0x91 /* DMA mode register chan 0rx */ 131 #define HD_DMR_0T 0xb1 /* DMA mode register chan 0tx */ 132 #define HD_DMR_1R 0xd1 /* DMA mode register chan 1rx */ 133 #define HD_DMR_1T 0xf1 /* DMA mode register chan 1tx */ 134 #define HD_FCT_0R 0x93 /* end-of-frame intr counter chan 0rx, ro */ 135 #define HD_FCT_0T 0xb3 /* end-of-frame intr counter chan 0tx, ro */ 136 #define HD_FCT_1R 0xd3 /* end-of-frame intr counter chan 1rx, ro */ 137 #define HD_FCT_1T 0xf3 /* end-of-frame intr counter chan 1tx, ro */ 138 #define HD_DIR_0R 0x94 /* DMA interrupt enable register chan 0rx */ 139 #define HD_DIR_0T 0xb4 /* DMA interrupt enable register chan 0tx */ 140 #define HD_DIR_1R 0xd4 /* DMA interrupt enable register chan 1rx */ 141 #define HD_DIR_1T 0xf4 /* DMA interrupt enable register chan 1tx */ 142 #define HD_DCR_0R 0x95 /* DMA command register chan 0rx, wo */ 143 #define HD_DCR_0T 0xb5 /* DMA command register chan 0tx, wo */ 144 #define HD_DCR_1R 0xd5 /* DMA command register chan 1rx, wo */ 145 #define HD_DCR_1T 0xf5 /* DMA command register chan 1tx, wo */ 146 147 /* 148 * Timer registers. 149 */ 150 #define HD_TCNT_0R 0x60 /* timer up counter chan 0rx */ 151 #define HD_TCNT_0T 0x68 /* timer up counter chan 0tx */ 152 #define HD_TCNT_1R 0x70 /* timer up counter chan 1rx */ 153 #define HD_TCNT_1T 0x78 /* timer up counter chan 1tx */ 154 #define HD_TCONR_0R 0x62 /* timer constant register chan 0rx, wo */ 155 #define HD_TCONR_0T 0x6a /* timer constant register chan 0tx, wo */ 156 #define HD_TCONR_1R 0x72 /* timer constant register chan 1rx, wo */ 157 #define HD_TCONR_1T 0x7a /* timer constant register chan 1tx, wo */ 158 #define HD_TCSR_0R 0x64 /* timer control/status register chan 0rx */ 159 #define HD_TCSR_0T 0x6c /* timer control/status register chan 0tx */ 160 #define HD_TCSR_1R 0x74 /* timer control/status register chan 1rx */ 161 #define HD_TCSR_1T 0x7c /* timer control/status register chan 1tx */ 162 #define HD_TEPR_0R 0x65 /* timer expand prescale register chan 0rx */ 163 #define HD_TEPR_0T 0x6d /* timer expand prescale register chan 0tx */ 164 #define HD_TEPR_1R 0x75 /* timer expand prescale register chan 1rx */ 165 #define HD_TEPR_1T 0x7d /* timer expand prescale register chan 1tx */ 166 167 /* 168 * Wait controller registers. 169 */ 170 #define HD_PABR0 0x02 /* physical address boundary register 0 */ 171 #define HD_PABR1 0x03 /* physical address boundary register 1 */ 172 #define HD_WCRL 0x04 /* wait control register L */ 173 #define HD_WCRM 0x05 /* wait control register M */ 174 #define HD_WCRH 0x06 /* wait control register H */ 175 176 /* 177 * Interrupt modified vector register (IMVR) bits. 178 */ 179 #define IMVR_CHAN1 040 /* channel 1 vector bit */ 180 #define IMVR_VECT_MASK 037 /* interrupt reason mask */ 181 182 #define IMVR_RX_RDY 004 /* receive buffer ready */ 183 #define IMVR_RX_INT 010 /* receive status */ 184 #define IMVR_RX_DMERR 024 /* receive DMA error */ 185 #define IMVR_RX_DMOK 026 /* receive DMA normal end */ 186 #define IMVR_RX_TIMER 034 /* timer 0/2 count match */ 187 188 #define IMVR_TX_RDY 006 /* transmit buffer ready */ 189 #define IMVR_TX_INT 012 /* transmit status */ 190 #define IMVR_TX_DMERR 030 /* transmit DMA error */ 191 #define IMVR_TX_DMOK 032 /* transmit DMA normal end */ 192 #define IMVR_TX_TIMER 036 /* timer 1/3 count match */ 193 194 /* 195 * Interrupt control register (ITCR) bits. 196 */ 197 #define ITCR_PRIO_DMAC 0x80 /* DMA priority higher than MSCI */ 198 #define ITCR_CYCLE_VOID 0x00 /* non-acknowledge cycle */ 199 #define ITCR_CYCLE_SINGLE 0x20 /* single acknowledge cycle */ 200 #define ITCR_CYCLE_DOUBLE 0x40 /* double acknowledge cycle */ 201 #define ITCR_VECT_MOD 0x10 /* interrupt modified vector flag */ 202 203 /* 204 * Interrupt status register 0 (ISR0) bits. 205 */ 206 #define ISR0_RX_RDY_0 0x01 /* channel 0 receiver ready */ 207 #define ISR0_TX_RDY_0 0x02 /* channel 0 transmitter ready */ 208 #define ISR0_RX_INT_0 0x04 /* channel 0 receiver status */ 209 #define ISR0_TX_INT_0 0x08 /* channel 0 transmitter status */ 210 #define ISR0_RX_RDY_1 0x10 /* channel 1 receiver ready */ 211 #define ISR0_TX_RDY_1 0x20 /* channel 1 transmitter ready */ 212 #define ISR0_RX_INT_1 0x40 /* channel 1 receiver status */ 213 #define ISR0_TX_INT_1 0x80 /* channel 1 transmitter status */ 214 215 /* 216 * Interrupt status register 1 (ISR1) bits. 217 */ 218 #define ISR1_RX_DMERR_0 0x01 /* channel 0 receive DMA error */ 219 #define ISR1_RX_DMOK_0 0x02 /* channel 0 receive DMA finished */ 220 #define ISR1_TX_DMERR_0 0x04 /* channel 0 transmit DMA error */ 221 #define ISR1_TX_DMOK_0 0x08 /* channel 0 transmit DMA finished */ 222 #define ISR1_RX_DMERR_1 0x10 /* channel 1 receive DMA error */ 223 #define ISR1_RX_DMOK_1 0x20 /* channel 1 receive DMA finished */ 224 #define ISR1_TX_DMERR_1 0x40 /* channel 1 transmit DMA error */ 225 #define ISR1_TX_DMOK_1 0x80 /* channel 1 transmit DMA finished */ 226 227 /* 228 * Interrupt status register 2 (ISR2) bits. 229 */ 230 #define ISR2_RX_TIMER_0 0x10 /* channel 0 receive timer */ 231 #define ISR2_TX_TIMER_0 0x20 /* channel 0 transmit timer */ 232 #define ISR2_RX_TIMER_1 0x40 /* channel 1 receive timer */ 233 #define ISR2_TX_TIMER_1 0x80 /* channel 1 transmit timer */ 234 235 /* 236 * Interrupt enable register 0 (IER0) bits. 237 */ 238 #define IER0_RX_RDYE_0 0x01 /* channel 0 receiver ready enable */ 239 #define IER0_TX_RDYE_0 0x02 /* channel 0 transmitter ready enable */ 240 #define IER0_RX_INTE_0 0x04 /* channel 0 receiver status enable */ 241 #define IER0_TX_INTE_0 0x08 /* channel 0 transmitter status enable */ 242 #define IER0_RX_RDYE_1 0x10 /* channel 1 receiver ready enable */ 243 #define IER0_TX_RDYE_1 0x20 /* channel 1 transmitter ready enable */ 244 #define IER0_RX_INTE_1 0x40 /* channel 1 receiver status enable */ 245 #define IER0_TX_INTE_1 0x80 /* channel 1 transmitter status enable */ 246 #define IER0_MASK_0 0x0f /* channel 0 bits */ 247 #define IER0_MASK_1 0xf0 /* channel 1 bits */ 248 249 /* 250 * Interrupt enable register 1 (IER1) bits. 251 */ 252 #define IER1_RX_DMERE_0 0x01 /* channel 0 receive DMA error enable */ 253 #define IER1_RX_DME_0 0x02 /* channel 0 receive DMA finished enable */ 254 #define IER1_TX_DMERE_0 0x04 /* channel 0 transmit DMA error enable */ 255 #define IER1_TX_DME_0 0x08 /* channel 0 transmit DMA finished enable */ 256 #define IER1_RX_DMERE_1 0x10 /* channel 1 receive DMA error enable */ 257 #define IER1_RX_DME_1 0x20 /* channel 1 receive DMA finished enable */ 258 #define IER1_TX_DMERE_1 0x40 /* channel 1 transmit DMA error enable */ 259 #define IER1_TX_DME_1 0x80 /* channel 1 transmit DMA finished enable */ 260 #define IER1_MASK_0 0x0f /* channel 0 bits */ 261 #define IER1_MASK_1 0xf0 /* channel 1 bits */ 262 263 /* 264 * Interrupt enable register 2 (IER2) bits. 265 */ 266 #define IER2_RX_TME_0 0x10 /* channel 0 receive timer enable */ 267 #define IER2_TX_TME_0 0x20 /* channel 0 transmit timer enable */ 268 #define IER2_RX_TME_1 0x40 /* channel 1 receive timer enable */ 269 #define IER2_TX_TME_1 0x80 /* channel 1 transmit timer enable */ 270 #define IER2_MASK_0 0x30 /* channel 0 bits */ 271 #define IER2_MASK_1 0xc0 /* channel 1 bits */ 272 273 /* 274 * Control register (CTL) bits. 275 */ 276 #define CTL_RTS_INV 0x01 /* RTS control bit (inverted) */ 277 #define CTL_SYNCLD 0x04 /* load SYN characters */ 278 #define CTL_BRK 0x08 /* async: send break */ 279 #define CTL_IDLE_MARK 0 /* HDLC: when idle, transmit mark */ 280 #define CTL_IDLE_PTRN 0x10 /* HDLC: when idle, transmit an idle pattern */ 281 #define CTL_UDRN_ABORT 0 /* HDLC: on underrun - abort */ 282 #define CTL_UDRN_FCS 0x20 /* HDLC: on underrun - send FCS/flag */ 283 284 /* 285 * Command register (CMD) values. 286 */ 287 #define CMD_TX_RESET 001 /* reset: disable, clear buffer/status/BRK */ 288 #define CMD_TX_ENABLE 002 /* transmitter enable */ 289 #define CMD_TX_DISABLE 003 /* transmitter disable */ 290 #define CMD_TX_CRC_INIT 004 /* initialize CRC calculator */ 291 #define CMD_TX_EOM_CHAR 006 /* set end-of-message char */ 292 #define CMD_TX_ABORT 007 /* abort transmission (HDLC mode) */ 293 #define CMD_TX_MPON 010 /* transmit char with MP bit on (async) */ 294 #define CMD_TX_CLEAR 011 /* clear the transmit buffer */ 295 296 #define CMD_RX_RESET 021 /* reset: disable, clear buffer/status */ 297 #define CMD_RX_ENABLE 022 /* receiver enable */ 298 #define CMD_RX_DISABLE 023 /* receiver disable */ 299 #define CMD_RX_CRC_INIT 024 /* initialize CRC calculator */ 300 #define CMD_RX_REJECT 025 /* reject current message (sync mode) */ 301 #define CMD_RX_SRCH_MP 026 /* skip all until the char witn MP bit on */ 302 303 #define CMD_NOOP 000 /* continue current operation */ 304 #define CMD_CHAN_RESET 041 /* init registers, disable/clear RX/TX */ 305 #define CMD_SEARCH_MODE 061 /* set the ADPLL to search mode */ 306 307 /* 308 * Status register 0 (ST0) bits. 309 */ 310 #define ST0_RX_RDY 0x01 /* receiver ready */ 311 #define ST0_TX_RDY 0x02 /* transmitter ready */ 312 #define ST0_RX_INT 0x40 /* receiver status interrupt */ 313 #define ST0_TX_INT 0x80 /* transmitter status interrupt */ 314 315 /* 316 * Status register 1 (ST1) bits. 317 */ 318 #define ST1_CDCD 0x04 /* carrier changed */ 319 #define ST1_CCTS 0x08 /* CTS changed */ 320 #define ST1_IDL 0x40 /* transmitter idle, ro */ 321 322 #define ST1_ASYNC_BRKE 0x01 /* break end detected */ 323 #define ST1_ASYNC_BRKD 0x02 /* break start detected */ 324 #define ST1_ASYNC_BITS "\20\1brke\2brkd\3cdcd\4ccts\7idl" 325 326 #define ST1_HDLC_IDLD 0x01 /* idle sequence start detected */ 327 #define ST1_HDLC_ABTD 0x02 /* abort sequence start detected */ 328 #define ST1_HDLC_FLGD 0x10 /* flag detected */ 329 #define ST1_HDLC_UDRN 0x80 /* underrun detected */ 330 #define ST1_HDLC_BITS "\20\1idld\2abtd\3cdcd\4ccts\5flgd\7idl\10udrn" 331 332 /* 333 * Status register 2 (ST2) bits. 334 */ 335 #define ST2_OVRN 0x08 /* overrun error detected */ 336 337 #define ST2_ASYNC_FRME 0x10 /* framing error detected */ 338 #define ST2_ASYNC_PE 0x20 /* parity error detected */ 339 #define ST2_ASYNC_PMP 0x40 /* parity/MP bit = 1 */ 340 #define ST2_ASYNC_BITS "\20\4ovrn\5frme\6pe\7pmp" 341 342 #define ST2_HDLC_CRCE 0x04 /* CRC error detected */ 343 #define ST2_HDLC_RBIT 0x10 /* residual bit frame detected */ 344 #define ST2_HDLC_ABT 0x20 /* frame with abort end detected */ 345 #define ST2_HDLC_SHRT 0x40 /* short frame detected */ 346 #define ST2_HDLC_EOM 0x80 /* receive frame end detected */ 347 #define ST2_HDLC_BITS "\20\3crce\4ovrn\5rbit\6abt\7shrt\10eom" 348 349 /* 350 * Status register 3 (ST3) bits. 351 */ 352 #define ST3_RX_ENABLED 0x01 /* receiver is enabled */ 353 #define ST3_TX_ENABLED 0x02 /* transmitter is enabled */ 354 #define ST3_DCD_INV 0x04 /* DCD input line inverted */ 355 #define ST3_CTS_INV 0x08 /* CTS input line inverted */ 356 #define ST3_ASYNC_BITS "\20\1rx\2tx\3nodcd\4nocts" 357 358 #define ST3_HDLC_SEARCH 0x10 /* ADPLL search mode */ 359 #define ST3_HDLC_TX 0x20 /* channel is transmitting data */ 360 #define ST3_HDLC_BITS "\20\1rx\2tx\3nodcd\4nocts\5search\6txact" 361 362 /* 363 * Frame status register (FST) bits, HDLC mode only. 364 */ 365 #define FST_CRCE 0x04 /* CRC error detected */ 366 #define FST_OVRN 0x08 /* overrun error detected */ 367 #define FST_RBIT 0x10 /* residual bit frame detected */ 368 #define FST_ABT 0x20 /* frame with abort end detected */ 369 #define FST_SHRT 0x40 /* short frame detected */ 370 #define FST_EOM 0x80 /* frame end flag */ 371 372 #define FST_EOT 0x01 /* end of transfer, transmit only */ 373 374 /* 375 * Interrupt enable register 0 (IE0) bits. 376 */ 377 #define IE0_RX_RDYE 0x01 /* receiver ready interrupt enable */ 378 #define IE0_TX_RDYE 0x02 /* transmitter ready interrupt enable */ 379 #define IE0_RX_INTE 0x40 /* receiver status interrupt enable */ 380 #define IE0_TX_INTE 0x80 /* transmitter status interrupt enable */ 381 382 /* 383 * Interrupt enable register 1 (IE1) bits. 384 */ 385 #define IE1_CDCDE 0x04 /* carrier changed */ 386 #define IE1_CCTSE 0x08 /* CTS changed */ 387 #define IE1_IDLE 0x40 /* transmitter idle, ro */ 388 389 #define IE1_ASYNC_BRKEE 0x01 /* break end detected */ 390 #define IE1_ASYNC_BRKDE 0x02 /* break start detected */ 391 392 #define IE1_HDLC_IDLDE 0x01 /* idle sequence start detected */ 393 #define IE1_HDLC_ABTDE 0x02 /* abort sequence start detected */ 394 #define IE1_HDLC_FLGDE 0x10 /* flag detected */ 395 #define IE1_HDLC_UDRNE 0x80 /* underrun detected */ 396 397 /* 398 * Interrupt enable register 2 (IE2) bits. 399 */ 400 #define IE2_OVRNE 0x08 /* overrun error detected */ 401 402 #define IE2_ASYNC_FRMEE 0x10 /* framing error detected */ 403 #define IE2_ASYNC_PEE 0x20 /* parity error detected */ 404 #define IE2_ASYNC_PMPE 0x40 /* parity/MP bit = 1 */ 405 406 #define IE2_HDLC_CRCEE 0x04 /* CRC error detected */ 407 #define IE2_HDLC_RBITE 0x10 /* residual bit frame detected */ 408 #define IE2_HDLC_ABTE 0x20 /* frame with abort end detected */ 409 #define IE2_HDLC_SHRTE 0x40 /* short frame detected */ 410 #define IE2_HDLC_EOME 0x80 /* receive frame end detected */ 411 412 /* 413 * Frame interrupt enable register (FIE) bits, HDLC mode only. 414 */ 415 #define FIE_EOMFE 0x80 /* receive frame end detected */ 416 417 /* 418 * Current status register (CST0,CST1) bits. 419 * For other bits, see ST2. 420 */ 421 #define CST0_CDE 0x0001 /* data present on top of FIFO */ 422 #define CST1_CDE 0x0100 /* data present on second stage of FIFO */ 423 424 /* 425 * Receive/transmit clock source register (RXS/TXS) bits. 426 */ 427 #define CLK_MASK 0x70 /* RXC/TXC clock input mask */ 428 #define CLK_LINE 0x00 /* RXC/TXC line input */ 429 #define CLK_INT 0x40 /* internal baud rate generator */ 430 431 #define CLK_RXS_LINE_NS 0x20 /* RXC line with noise suppression */ 432 #define CLK_RXS_DPLL_INT 0x60 /* ADPLL based on internal BRG */ 433 #define CLK_RXS_DPLL_LINE 0x70 /* ADPLL based on RXC line */ 434 435 #define CLK_TXS_RECV 0x60 /* receive clock */ 436 437 /* 438 * DMA status register (DSR) bits. 439 */ 440 #define DSR_DMA_DISABLE 0x00 /* disable DMA channel */ 441 #define DSR_DMA_ENABLE 0x02 /* enable DMA channel */ 442 #define DSR_DMA_CONTINUE 0x01 /* do not enable/disable DMA channel */ 443 #define DSR_CHAIN_COF 0x10 /* counter overflow */ 444 #define DSR_CHAIN_BOF 0x20 /* buffer overflow/underflow */ 445 #define DSR_CHAIN_EOM 0x40 /* frame transfer completed */ 446 #define DSR_EOT 0x80 /* transfer completed */ 447 #define DSR_BITS "\20\1cont\2enab\5cof\6bof\7eom\10eot" 448 449 /* 450 * DMA mode register (DMR) bits. 451 */ 452 #define DMR_CHAIN_CNTE 0x02 /* enable frame interrupt counter (FCT) */ 453 #define DMR_CHAIN_NF 0x04 /* multi-frame block chain */ 454 #define DMR_TMOD 0x10 /* chained-block transfer mode */ 455 456 /* 457 * DMA interrupt enable register (DIR) bits. 458 */ 459 #define DIR_CHAIN_COFE 0x10 /* counter overflow */ 460 #define DIR_CHAIN_BOFE 0x20 /* buffer overflow/underflow */ 461 #define DIR_CHAIN_EOME 0x40 /* frame transfer completed */ 462 #define DIR_EOTE 0x80 /* transfer completed */ 463 464 /* 465 * DMA command register (DCR) values. 466 */ 467 #define DCR_ABORT 1 /* software abort: initialize DMA channel */ 468 #define DCR_CLEAR 2 /* clear FCT and EOM bit of DSR */ 469 470 /* 471 * DMA master enable register (DME) bits. 472 */ 473 #define DME_ENABLE 0x80 /* enable DMA master operation */ 474 475 /* 476 * Timer control/status register (TCSR) bits. 477 */ 478 #define TCSR_ENABLE 0x10 /* timer starts incrementing */ 479 #define TCSR_INTR 0x40 /* timer interrupt enable */ 480 #define TCSR_MATCH 0x80 /* TCNT and TCONR are equal */ 481 482 /* 483 * Timer expand prescale register (TEPR) values. 484 */ 485 #define TEPR_1 0 /* sysclk/8 */ 486 #define TEPR_2 1 /* sysclk/8/2 */ 487 #define TEPR_4 2 /* sysclk/8/4 */ 488 #define TEPR_8 3 /* sysclk/8/8 */ 489 #define TEPR_16 4 /* sysclk/8/16 */ 490 #define TEPR_32 5 /* sysclk/8/32 */ 491 #define TEPR_64 6 /* sysclk/8/64 */ 492 #define TEPR_128 7 /* sysclk/8/128 */ 493