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Searched refs:SUBREG_TO_REG (Results 1 – 21 of 21) sorted by relevance

/freebsd-10-stable/contrib/llvm/lib/Target/X86/
DX86InstrExtension.td152 // 64-bit zero-extension patterns use SUBREG_TO_REG and an operation writing a
155 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8:$src), sub_32bit)>;
157 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
160 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16:$src), sub_32bit)>;
162 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
165 // SUBREG_TO_REG to utilize implicit zero-extension, however this isn't possible
170 (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src), sub_32bit)>;
172 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
DX86InstrCompiler.td233 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
238 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
252 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
1115 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1132 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1134 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1136 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1138 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1151 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1153 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
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DX86InstrAVX512.td674 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
675 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
681 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
682 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
712 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
713 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
717 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
718 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
801 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
802 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
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DX86InstrSSE.td453 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
455 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
457 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
459 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
461 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
463 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
465 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
467 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
572 (SUBREG_TO_REG (i32 0),
576 (SUBREG_TO_REG (i32 0),
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DX86ISelDAGToDAG.cpp1434 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64, in SelectLEA64_32Addr()
1448 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64, in SelectLEA64_32Addr()
2514 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64, in Select()
DX86FastISel.cpp1104 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::SUBREG_TO_REG), in X86SelectZExt()
1437 TII.get(TargetOpcode::SUBREG_TO_REG), TypeEntry.HighInReg) in X86SelectDivRem()
DX86ISelLowering.cpp15083 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) in EmitVAARG64WithCustomInserter()
/freebsd-10-stable/contrib/llvm/include/llvm/Target/
DTargetOpcodes.h58 SUBREG_TO_REG = 9, enumerator
DTarget.td753 def SUBREG_TO_REG : Instruction {
/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/
DAArch64InstrNEON.td2139 (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2144 (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2149 (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2165 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2171 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2177 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2682 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2689 (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
3694 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
3777 (SUBREG_TO_REG (i64 0), VPR64:$Rt, sub_64),
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DAArch64ISelDAGToDAG.cpp271 ResNode = CurDAG->getMachineNode(TargetOpcode::SUBREG_TO_REG, dl, in TrySelectToMoveImm()
798 SDNode *Reg = CurDAG->getMachineNode(TargetOpcode::SUBREG_TO_REG, DL, in getTargetSubregToReg()
DAArch64InstrInfo.td1277 (SBFXxxii (SUBREG_TO_REG (i64 0), $Rn, sub_32), 0, 0)>;
1281 def : Pat<(i64 (zext i32:$Rn)), (SUBREG_TO_REG (i64 0), (UBFXwwii $Rn, 0, 31),
4641 (SUBREG_TO_REG (i64 0),
4805 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
4808 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>;
4993 (SUBREG_TO_REG (i64 0), (LS32_LDUR Base, Offset), sub_32)>;
5044 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
5047 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>;
/freebsd-10-stable/contrib/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp209 case TargetOpcode::SUBREG_TO_REG: in runOnMachineFunction()
DPeepholeOptimizer.cpp236 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG) in INITIALIZE_PASS_DEPENDENCY()
/freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/
DMachineInstr.h661 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
699 case TargetOpcode::SUBREG_TO_REG:
/freebsd-10-stable/contrib/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp266 case TargetOpcode::SUBREG_TO_REG: in isResourceAvailable()
306 case TargetOpcode::SUBREG_TO_REG: in reserveResources()
DInstrEmitter.cpp527 Opc == TargetOpcode::SUBREG_TO_REG) { in EmitSubregNode()
560 if (Opc == TargetOpcode::SUBREG_TO_REG) { in EmitSubregNode()
717 Opc == TargetOpcode::SUBREG_TO_REG) { in EmitMachineNode()
DScheduleDAGRRList.cpp1898 Opc == TargetOpcode::SUBREG_TO_REG || in getNodePriority()
2119 Opc == TargetOpcode::SUBREG_TO_REG || in unscheduledNode()
2148 POpc == TargetOpcode::SUBREG_TO_REG) { in unscheduledNode()
2590 Opc == TargetOpcode::SUBREG_TO_REG || in canEnableCoalescing()
2963 SuccOpc == TargetOpcode::SUBREG_TO_REG) in AddPseudoTwoAddrDeps()
/freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp55 case TargetOpcode::SUBREG_TO_REG: in isResourceAvailable()
107 case TargetOpcode::SUBREG_TO_REG: in reserveResources()
/freebsd-10-stable/contrib/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td304 // we can use a SUBREG_TO_REG.
306 (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>;
1131 (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>;
/freebsd-10-stable/contrib/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp2813 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) in emitINSERT_FW()
2846 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) in emitINSERT_FD()