| /freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 195 ADDC, SUBC, enumerator
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| /freebsd-10-stable/contrib/llvm/patches/ |
| D | patch-r262261-llvm-r198281-sparc.diff | 77 case ISD::SUBC:
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| /freebsd-10-stable/contrib/llvm/lib/Target/R600/ |
| D | AMDILISelLowering.cpp | 101 setOperationAction(ISD::SUBC, VT, Expand); in InitAMDILLowering()
195 setOperationAction(ISD::SUBC, MVT::Other, Expand); in InitAMDILLowering()
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| /freebsd-10-stable/contrib/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 258 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in selectNode()
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| D | MipsSEISelDAGToDAG.cpp | 237 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in selectAddESubE()
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| D | MipsSEISelLowering.cpp | 370 if (SUBCNode->getOpcode() != ISD::SUBC) in selectMSUB()
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| /freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1411 setOperationAction(ISD::SUBC, MVT::i8, Expand); in HexagonTargetLowering()
1412 setOperationAction(ISD::SUBC, MVT::i16, Expand); in HexagonTargetLowering()
1413 setOperationAction(ISD::SUBC, MVT::i32, Expand); in HexagonTargetLowering()
1414 setOperationAction(ISD::SUBC, MVT::i64, Expand); in HexagonTargetLowering()
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| /freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 83 SUBC, // Sub with carry enumerator
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| D | ARMISelLowering.cpp | 662 setOperationAction(ISD::SUBC, MVT::i32, Custom); in ARMTargetLowering()
1048 case ARMISD::SUBC: return "ARMISD::SUBC"; in getTargetNodeName()
5954 case ISD::SUBC: Opc = ARMISD::SUBC; break; in LowerADDC_ADDE_SUBC_SUBE()
6156 case ISD::SUBC: in LowerOperation()
10728 case ARMISD::SUBC: in computeMaskedBitsForTargetNode()
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| D | ARMInstrInfo.td | 157 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
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| /freebsd-10-stable/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 205 case ISD::SUBC: return "subc"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 1153 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; in ExpandIntegerResult()
1544 ISD::ADDC : ISD::SUBC, in ExpandIntRes_ADDSUB()
1554 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); in ExpandIntRes_ADDSUB()
1603 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); in ExpandIntRes_ADDSUBC()
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| D | TargetLowering.cpp | 1753 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { in SimplifySetCC() local
1757 DAG.getConstant(SUBC->getAPIntValue() - in SimplifySetCC()
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| D | DAGCombiner.cpp | 1129 case ISD::SUBC: return visitSUBC(N); in visit()
1776 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1); in visitSUBE()
3403 if (ConstantSDNode *SUBC = in MatchRotate() local
3405 if (SUBC->getAPIntValue() == OpSizeInBits) in MatchRotate()
3414 if (ConstantSDNode *SUBC = in MatchRotate() local
3416 if (SUBC->getAPIntValue() == OpSizeInBits) in MatchRotate()
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| /freebsd-10-stable/contrib/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1461 setOperationAction(ISD::SUBC, MVT::i64, Custom); in SparcTargetLowering()
2702 case ISD::SUBC: hiOpc = ISD::SUBE; break; in LowerADDC_ADDE_SUBC_SUBE()
2835 case ISD::SUBC: in LowerOperation()
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| /freebsd-10-stable/contrib/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 345 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
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| /freebsd-10-stable/contrib/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 94 setOperationAction(ISD::SUBC, MVT::i32, Expand); in XCoreTargetLowering()
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| /freebsd-10-stable/contrib/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 431 setOperationAction(ISD::SUBC, VT, Custom); in resetOperationActions()
13334 case ISD::SUBC: Opc = X86ISD::SUB; break; in LowerADDC_ADDE_SUBC_SUBE()
13475 case ISD::SUBC: in LowerOperation()
13541 case ISD::SUBC: in ReplaceNodeResults()
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