Searched refs:RHS1 (Results 1 – 3 of 3) sorted by relevance
| /freebsd-10-stable/contrib/llvm/include/llvm/ADT/ |
| D | SparseBitVector.h | 250 void intersectWithComplement(const SparseBitVectorElement &RHS1,
257 Bits[i] = RHS1.Bits[i] & ~RHS2.Bits[i];
694 void intersectWithComplement(const SparseBitVector<ElementSize> &RHS1,
699 ElementListConstIter Iter1 = RHS1.Elements.begin();
704 if (RHS1.Elements.empty())
709 if (Iter1 == RHS1.Elements.end())
735 while (Iter1 != RHS1.Elements.end()) {
745 void intersectWithComplement(const SparseBitVector<ElementSize> *RHS1,
747 intersectWithComplement(*RHS1, *RHS2);
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| /freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 3524 SDValue RHS1, RHS2; in OptimizeVFPBrcond() local
3526 expandf64Toi32(RHS, DAG, RHS1, RHS2); in OptimizeVFPBrcond()
3532 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; in OptimizeVFPBrcond()
7873 unsigned RHS1 = MI->getOperand(3).getReg(); in EmitInstrWithCustomInserter() local
7877 .addReg(LHS1).addReg(RHS1)); in EmitInstrWithCustomInserter()
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| /freebsd-10-stable/contrib/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 9836 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); in Lower256IntVSETCC() local
9843 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), in Lower256IntVSETCC()
12421 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); in Lower256IntArith() local
12428 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), in Lower256IntArith()
16968 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL); in PerformSELECTCombine() local
16972 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1); in PerformSELECTCombine()
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