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Searched refs:RADEON_CP_CSQ_CNTL (Results 1 – 8 of 8) sorted by relevance

/freebsd-10-stable/sys/dev/drm2/radeon/
Dr100.c1193 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); in r100_cp_init()
1236 WREG32(RADEON_CP_CSQ_CNTL, 0); in r100_cp_disable()
2682 WREG32(RADEON_CP_CSQ_CNTL, 0); in r100_asic_reset()
4088 tmp = RREG32(RADEON_CP_CSQ_CNTL); in r100_restore_sanity()
4090 WREG32(RADEON_CP_CSQ_CNTL, 0); in r100_restore_sanity()
Dradeon_cp.c610 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); in radeon_do_cp_start()
676 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); in radeon_do_cp_stop()
Drs600.c409 WREG32(RADEON_CP_CSQ_CNTL, 0); in rs600_asic_reset()
Dr300.c397 WREG32(RADEON_CP_CSQ_CNTL, 0); in r300_asic_reset()
Dradeon_drv.h1053 #define RADEON_CP_CSQ_CNTL 0x0740 macro
Dradeon_reg.h3336 #define RADEON_CP_CSQ_CNTL 0x0740 macro
/freebsd-10-stable/sys/dev/drm/
Dradeon_cp.c578 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); in radeon_do_cp_start()
621 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); in radeon_do_cp_stop()
Dradeon_drv.h1131 #define RADEON_CP_CSQ_CNTL 0x0740 macro